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| Freescale Semiconductor Advance Information Document Number: MCIMX31 Rev. 1.4, 04/2006 MCIMX31 and MCIMX31L i.MX31 and i.MX31L Multimedia Applications Processors Package Information Plastic Package Case 1581-01 14 x 14 mm, 0.5 P Ordering Information Device MCIMX31VKN5 MCIMX31LVKN5 Operating Temperature Range 0C to +70C 0C to +70C Package MAPBGA-457 MAPBGA-457 1 Introduction Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . 2 2 Functional Description and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 ARM11 Microprocessor Core . . . . . . . . . . . 3 2.2 Module Inventory . . . . . . . . . . . . . . . . . . . . 5 2.3 Module Descriptions . . . . . . . . . . . . . . . . . . 8 3 Signal Descriptions . . . . . . . . . . . . . . . . . . . 23 3.1 i.MX31 and i.MX31L I/O Pad Signal Settings . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4 Electrical Characteristics . . . . . . . . . . . . . . 60 4.1 i.MX31 and i.MX31L Chip-Level Conditions . . . . . . . . . . . . . . . 60 4.2 Supply Power-Up Requirements and Restrictions . . . . . . . . . . . . . . . . . . . . . . . 65 4.3 Module-Level Electrical Specifications . . . 66 5 Package Information and Pinout . . . . . . . 152 5.1 MAPBGA Production Package 457 14 x 14 mm, 0.5 P . . . . . . . . . . . . . . 153 6 Product Documentation . . . . . . . . . . . . . . . 167 6.1 Revision History . . . . . . . . . . . . . . . . . . . 167 The i.MX31 (MCIMX31) and i.MX31L (MCIMX31L) are multimedia applications processors that represent the next step in low-power, high-performance application processors. Unless otherwise specified, the material in this data sheet is applicable to both the i.MX31 and i.MX31L processors. Based on an ARM11TM microprocessor core, the i.MX31 and i.MX31L provide the performance with low power consumption required by modern digital devices such as: * Feature-rich cellular phones * Portable media players and mobile gaming machines * Personal digital assistants (PDAs) and Wireless PDAs * Portable DVD players * Digital cameras The i.MX31 and i.MX31L take advantage of the ARM1136JF-STM core running at typical speeds of 532 MHz, and is optimized for minimal power This document contains information on a new product. Specifications and information herein are subject to change without notice. (c) Freescale Semiconductor, Inc., 2005, 2006. All rights reserved. Preliminary Introduction consumption using the most advanced techniques for power saving (DPTC, DVFS, power gating, clock gating). With 90 nm technology and dual-Vt transistors (two threshold voltages), the i.MX31 and i.MX31L provide the optimal performance versus leakage current balance. The performance of the i.MX31 and i.MX31L is boosted by a multi-level cache system, and features peripheral devices such as an MPEG-4 Hardware Encoder (VGA, 30 fps), an Autonomous Image Processing Unit, a Vector Floating Point (VFP11) co-processor, and a RISC-based SDMA controller. The i.MX31 and i.MX31L support connections to various types of external memories, such as 266 MHz DDR, NAND Flash, NOR Flash, SDRAM, and SRAM. The i.MX31 and i.MX31L can be connected to a variety of external devices using technology, such as high-speed USB2.0 OTG, ATA, MMC/SDIO, and compact flash. 1.1 Features The i.MX31 and i.MX31L are designed for the high-tier and mid-tier smartphone markets. They provide low-power solutions for high-performance demanding multimedia and graphics applications. The i.MX31 and i.MX31L are built around the ARM11 MCU core and implemented in the 90 nm technology. The systems include the following features: * Multimedia and floating-point hardware acceleration supporting: -- MPEG-4 real-time encode of up to VGA at 30 fps -- MPEG-4 real-time video post-processing of up to VGA at 30 fps -- Video conference call of up to QCIF-30 fps (decoder in software), 128 kbps -- Video streaming (playback) of up to VGA-30 fps, 384 kbps -- 3D graphics and other applications acceleration with the ARM(R) tightly-coupled Vector Floating Point co-processor -- On-the-fly video processing that reduces system memory load (for example, the power-efficient viewfinder application with no involvement of either the memory system or the ARM CPU) * Advanced power management -- Dynamic voltage and frequency scaling -- Multiple clock and power domains -- Independent gating of power domains * Multiple communication and expansion ports including a fast parallel interface to an external graphic accelerator (supporting major graphic accelerator vendors) 1.2 Block Diagram Figure 1 shows the i.MX31 and i.MX31L simplified interface block diagram. i.MX31/i.MX31L Advance Information, Rev. 1.4 2 Preliminary Freescale Semiconductor Functional Description and Application Information SRAM, PSRAM, NOR Flash SDRAM DDR NAND Flash, SmartMedia Camera Sensor (2) Parallel Display (2) Serial LCD Tamper Detection Mouse Keyboard External Memory Interface (EMI) MPEG-4 Video Encoder Image Processing Unit (IPU) Inversion and Rotation Camera Interface Blending SDMA Display/TV Ctl Pre & Post Processing Internal Memory Expansion SDHC (2) PCMCIA/CF Mem Stick (2) SIM ATA Debug ECT SJC Security SCC RTIC RNGA GPS * GPU unavailable for i.MX31L ATA Hard Drive Timers RTC WDOG GPT EPIT (2) AP Peripherals AUDMUX SSI (2) UART (5) I2C (3) FIR CSPI (3) PWM USB Host (2) USB-OTG KPP GPIO CCM 1-WIRE(R) IIM GPU* Power Management IC ARM11TM Platform ARM1136JF-S I-Cache D-Cache L2-Cache MAX ROMPATCH VFP TM 8x8 Keypad Serial EPROM ETM Fast IrDA Bluetooth Baseband WLAN SD Card PC Card PC Card USB Host/Device Figure 1. i.MX31/i.MX31L Simplified Interface Block Diagram Table 1 provides additional details on the i.MX31 and i.MX31L orderable parts. Table 1. Orderable Part Details Device MCIMX31VKN5 MCIMX31LVKN5 Operating Temp. Range (TA) -0C to +70C -0C to +70C Package 457-lead MAPBGA 0.5 mm, 14 mm x 14 mm 457-lead MAPBGA 0.5 mm, 14 mm x 14 mm RoHS Compliant Yes Yes Pb-Free Yes Yes MSL Level 3 3 Solder Temp. 260C 260C 2 2.1 Functional Description and Application Information ARM11 Microprocessor Core The CPU of the i.MX31 and i.MX31L is the ARM1136JF-S core based on the ARM v6 architecture. It supports the ARM Thumb(R) instruction sets, features Jazelle(R) technology (which enables direct execution of Java byte codes), and a range of SIMD DSP instructions that operate on 16-bit or 8-bit data values in 32-bit registers. i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 3 Functional Description and Application Information The ARM1136JF-S processor core features: * Integer unit with integral EmbeddedICETM logic * Eight-stage pipeline * Branch prediction with return stack * Low-interrupt latency * Instruction and data memory management units (MMUs), managed using micro TLB structures backed by a unified main TLB * Instruction and data L1 caches, including a non-blocking data cache with Hit-Under-Miss * Virtually indexed/physically addressed L1 caches * 64-bit interface to both L1 caches * Write buffer (bypassable) * High-speed Advanced Micro Bus Architecture (AMBA)TM L2 interface * Vector Floating Point co-processor (VFP) for 3D graphics and other floating-point applications hardware acceleration * ETMTM and JTAG-based debug support 2.1.1 Performance ARM1136JF-S operating frequency in C90LP process: * 532 MHz (4 x 133 MHz) (wcs) 2.1.2 Memory System The ARM1136JF-S complex includes 16 KB Instruction and 16 KB Data L1 caches. It connects to the i.MX31 and i.MX31L L2 unified cache through 64-bit instruction (read-only), 64-bit data read/write (bi-directional), and 64-bit data write interfaces. The embedded 16K SRAM can be used for audio streaming data to avoid external memory accesses for the Low Power Audio Playback, for Security, or for other applications. There is also a 32-KB ROM for bootstrap code and other frequently-used code and data. A ROM patch module provides the ability to patch the internal ROM. It can also initiate an external boot by overriding the boot reset sequence by a jump to a configurable address. Table 2 shows information about the i.MX31 and i.MX31L core in tabular form. i.MX31/i.MX31L Advance Information, Rev. 1.4 4 Preliminary Freescale Semiconductor Functional Description and Application Information Table 2. i.MX31/i.MX31L Core Core Acronym Core Name Brief Description The ARM1136TM Platform consists of the ARM1136JF-S core, the ETM real-time debug modules, a 6 x 5 multi-layer AHB crossbar switch (MAX), and a Vector Floating Processor (VFP). The i.MX31/i.MX31L provide a high-performance ARM11 microprocessor core and highly integrated system functions. The ARM Application Processor (AP) and other subsystems address the needs of the personal, wireless, and portable product market with integrated peripherals, advanced processor core, and power management capabilities. Integrated Memory Includes * 16 Kbyte Instruction Cache * 16 Kbyte Data Cache * 128 Kbyte L2 Cache * 32 Kbyte ROM * 16 Kbyte RAM ARM11 or ARM1136 ARM1136 Platform 2.2 Module Inventory Table 3 shows an alphabetical listing of the modules in the multimedia applications processor. A cross-reference is provided directly to each module description for more information. Table 3. Digital and Analog Modules Block Mnemonic 1-Wire(R) Block Name Functional Grouping Brief Description3 The 1-Wire module provides bi-directional communication between the ARM11 core and the Add-Only-Memory EPROM (DS2502). The 1-Kbit EPROM is used to hold information about battery and communicates with the ARM11 platform using the IP interface. The ATA block is an AT attachment host interface. It is designed to interface with IDE hard disc drives and ATAPI optical disc drives. The AUDMUX interconnections allow multiple, simultaneous audio/voice/data flows between the ports in point-to-point or point-to-multipoint configurations. The CCM provides clock, reset, and power management control for the i.MX31 and i.MX31L. The CSPI is equipped with data FIFOs and is a master/slave configurable serial peripheral interface module, capable of interfacing to both SPI master and slave devices. The ECT is composed of three CTIs (Cross Trigger Interface) and one CTM (Cross Trigger Matrix--key in the multi-core and multi-IP debug strategy. Section/ Page 2.3.1/8 1-Wire Interface Connectivity Peripheral ATA Advanced Connectivity Technology (AT) Peripheral Attachment Digital Audio Multiplexer Clock Control Module Multimedia Peripheral Clock 2.3.2/8 AUDMUX 2.3.3/9 CCM CSPI 2.3.4/9 2.3.5/10 Configurable Connectivity Serial Peripheral Peripheral Interface (x 3) Embedded Cross Trigger External Memory Interface Debug ECT 2.3.6/10 EMI Memory The EMI includes Interface (EMI) * Multi-Master Memory Interface (M3IF) * Enhanced SDRAM/MDDR memory controller (SDRAMC) * NAND Flash Controller (NFC) * Wireless External Interface Module (WEIM) Timer Peripheral The EPIT is a 32-bit "set and forget" timer which starts counting after the EPIT is enabled by software. It is capable of providing precise interrupts at regular intervals with minimal processor intervention. 2.3.7/11 EPIT Enhanced Periodic Interrupt Timer 2.3.8/12 i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 5 Functional Description and Application Information Table 3. Digital and Analog Modules (continued) Block Mnemonic FIR Block Name Fast InfraRed Interface Functional Grouping Connectivity Peripheral Brief Description3 This FIR is capable of establishing a 0.576 Mbit/s, 1.152 Mbit/s or 4 Mbit/s half duplex link via a LED and IR detector. It supports 0.576 Mbit/s, 1.152 Mbit/s medium infrared (MIR) physical layer protocol and 4Mbit/s fast infrared (FIR) physical layer protocol defined by IrDA, version 1.4. The GPIO provides 32 bits of bidirectional, general purpose I/O. This peripheral provides dedicated general-purpose pins that can be configured as either inputs or outputs. The GPT is a multipurpose module used to measure intervals or generate periodic output. The GPU provides hardware acceleration for 2D and 3D graphics algorithms. Section/ Page 2.3.9/12 GPIO General Purpose I/O Module General Purpose Timer Graphics Processing Unit Inter IC Communication IC Identification Module Image Processing Unit Keypad Port Pins 2.3.10/12 GPT GPU I2C Timer Peripheral Multimedia Peripheral Connectivity Peripheral Security 2.3.11/12 2.3.12/13 The I2C provides serial interface for controlling the Sensor Interface 2.3.13/13 and other external devices. Data rates of up to 100 Kbits/s are supported. The IIM provides an interface for reading--and in some cases, programming, and overriding identification and control information stored in on-chip fuse elements. The IPU supports video and graphics processing functions in the i.MX31 and i.MX31L and interfaces to video, still image sensors, and displays. 2.3.14/13 IIM IPU Multimedia Peripheral Connectivity Peripheral Multimedia Peripherals Connectivity Peripheral Timer Peripheral Security 2.3.15/14 KPP The KPP is used for key pad matrix scanning or as a general 2.3.16/15 purpose I/O. This peripheral simplifies the software task of scanning a keypad matrix. The MPEG-4 encoder accelerates video compression, following the 2.3.17/15 MPEG-4 standard The PCMCIA Host Adapter provides the control logic for PCMCIA socket interfaces. 2.3.19/16 MPEG-4 PCMCIA PWM RNGA MPEG-4 Video Encoder PCM Pulse-Width Modulator Random Number Generator Accelerator The PWM has a 16-bit counter and is optimized to generate sound 2.3.20/16 from stored sample audio images. It can also generate tones. The RNGA module is a digital integrated circuit capable of generating 32-bit random numbers. It is designed to comply with FIPS-140 standards for randomness and non-determinism. 2.3.21/16 RTC Real Time Clock Timer Peripheral Run-Time Integrity Checkers Security The RTC module provides a current stamp of seconds, minutes, 2.3.22/16 hours, and days. Alarm and timer functions are also available for programming. The RTC support dates from the year 1980 to 2050. The RTIC ensures the integrity of the peripheral memory contents and assists with boot authentication. 2.3.23/17 RTIC i.MX31/i.MX31L Advance Information, Rev. 1.4 6 Preliminary Freescale Semiconductor Functional Description and Application Information Table 3. Digital and Analog Modules (continued) Block Mnemonic SCC Block Name Security Controller Module Functional Grouping Security Brief Description3 Section/ Page The SCC is a hardware component composed of two blocks--the 2.3.24/17 Secure RAM module, and the Security Monitor. The Secure RAM provides a way of securely storing sensitive information. The Security Monitor implements the security policy, checking algorithm sequencing, and controlling the Secure State. The SDHC controls the MMC (MultiMediaCard), SD (Secure 2.3.25/18 Digital) memory, and I/O cards by sending commands to cards and performing data accesses to and from the cards. The SDMA controller maximizes the system's performance by 2.3.26/18 relieving the ARM core of the task of bulk data transfer from memory to memory or between memory and on-chip peripherals. The SIM interfaces to an external Subscriber Identification Card. It 2.3.27/20 is an asynchronous serial interface adapted for Smart Card communication for e-commerce applications. The SJC provides debug and test control with maximum security and provides a flexible architecture for future derivatives or future multi-cores architecture. 2.3.28/20 SDHC Secured Digital Host Controller SDMA Connectivity Peripheral System Control Peripheral Connectivity Peripheral Debug SDMA SIM Subscriber Identification Module Secure JTAG Controller Synchronous Serial Interface SJC SSI Multimedia Peripheral 2.3.29/20 The SSI is a full-duplex, serial port that allows the chip to communicate with a variety of serial devices, such as standard codecs, Digital Signal Processors (DSPs), microprocessors, peripherals, and popular industry audio codecs that implement the inter-IC sound bus standard (I2S) and Intel AC97 standard. The UART provides serial communication capability with external devices through an RS-232 cable or through use of external circuitry that converts infrared signals to electrical signals (for reception) or transforms electrical signals to signals that drive an infrared LED (for transmission) to provide low speed IrDA compatibility. 2.3.30/21 UART Universal Asynchronous Receiver/Trans mitter Connectivity Peripheral USB Universal Serial Bus-- 2 Host Controllers and 1 OTG (On-The-Go) Connectivity Peripherals * USB Host 1 is designed to support transceiverless connection to 2.3.31/21 the on-board peripherals in Low Speed and Full Speed mode, and connection to the ULPI (UTMI+ Low-Pin Count) and Legacy Full Speed transceivers. * USB Host 2 is designed to support transceiverless connection to the Cellular Modem Baseband Processor. * The USB-OTG controller offers HS/FS/LS capabilities in Host mode and HS/FS in device mode. In Host mode, the controller supports direct connection of a FS/LS device (without external hub). In device (bypass) mode, the OTG port functions as gateway between the Host 1 Port and the OTG transceiver. The WDOG module protects against system failures by providing a 2.3.32/23 method for the system to recover from unexpected events or programming errors. WDOG Watchdog Timer Timer Module Peripheral i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 7 Functional Description and Application Information 2.3 Module Descriptions This section provides a brief text description of all the modules included in the i.MX31 and i.MX31L, arranged in alphabetical order. 2.3.1 1-Wire The 1-Wire module provides bi-directional communication between the ARM11 core and the Add-Only-Memory EPROM (DS2502). The 1-Kbit EPROM is used to hold information about battery and communicates with the ARM11 platform using the IP interface. The ARM11 (through the 1-Wire interface) acts as the bus master and the DS2502 device is the slave. The 1-Wire peripheral does not trigger interrupts; hence it is necessary for the ARM11 to poll of the 1-Wire to manage the module. The 1-Wire uses an external pin(to connect to the DS2502. Timing requirements are met in hardware with the help of a 1 MHz clock. The clock divider generates a 1 MHz clock that is used as time reference by the state machine. Timing requirements are crucial for proper operation, and the 1-Wire state machine and the internal clock provide the necessary signal. The clock must configured to approximately 1 MHz. You can then set the 1-Wire register to send and receive bits over the 1-Wire bus. 2.3.2 Advanced Technology Attachment (ATA) The ATA block provides an AT attachment host interface for the i.MX31 and i.MX31L. Its main use is to provide an interface with IDE hard disc drives and ATAPI optical disc drives. It interfaces with the ATA device using industry standard ATA signals. The ATA interface is compliant to the ATA standard, and supports following ATA standard protocols: * * * * PIO modes 0, 1, 2, 3, and 4 Multiword DMA modes 0, 1, and 2 Ultra DMA modes 0, 1, 2, 3, and 4 with a bus clock of 50 MHz or higher Ultra DMA mode 5 with bus clock of 80 MHz or higher The ATA interface has two busses connected to it. The CPU bus provides communication with the ARM11 host processor and the DMA bus provides communication between the ATA module and the host DMA unit. All internal ATA registers are visible from both busses, allowing enhanced DMA access to program the interface. There are basically two protocols that can be active at the same time on the ATA bus. The first and simplest protocol (PIO mode access) can be started at any time by either the ARM11 or the host-enhanced DMA to the ATA bus. The PIO mode is a slow protocol, mainly intended to be used to program an ATA disc drive, but also possible to use to transfer data to/from the disc drive. The second protocol is the DMA mode access. DMA mode is started by the ATA interface after receiving a DMA request from the drive, and only if the ATA interface has been programmed to accept the DMA request. In DMA mode, either multiword DMA or ultra DMA protocol is used on the ATA bus. All transfers between FIFO and host IP or DMA IP bus are zero wait states transfer, so high speed transfer between FIFO and DMA/host bus is possible. i.MX31/i.MX31L Advance Information, Rev. 1.4 8 Preliminary Freescale Semiconductor Functional Description and Application Information 2.3.3 Digital Audio Mux (AUDMUX) The AUDMUX provides programmable interconnecting for voice, audio, and synchronous data routing between host serial interfaces (i.e. SSI, SAP) and peripheral serial interfaces (i.e. audio and voice codecs). The AUDMUX allows audio system connectivity to be modified through programming (as opposed to altering the design of the system into which the chip is designed). The design of the AUDMUX allows multiple simultaneous audio/voice/data flows between the ports in point-to-point or point-to-multipoint configurations. Included in the AUDMUX are two types of interfaces. The internal ports connect to the processor serial interfaces and external ports connect to off-chip audio devices and serial interfaces of other processors. A desired connectivity is achieved by configuring the appropriate internal and external ports. The module includes full 6-wire SSI interfaces for asynchronous receive and transmit as well as a configurable 4-wire (synchronous) or 6-wire (asynchronous) peripheral interface The AUDMUX allows each host interface to be connected to any other host or peripheral interface in a point-to-point or point-to-multipoint (network mode). 2.3.4 Clock Control Module (CCM) The CCM controls the system frequency, distributes clocks to various parts of the chip, controls the reset mechanism of the chip, and provides an advanced low-power management capability of the i.MX31 and i.MX31L. The CCM utilizes multiple clock sources to generate the clock signals in the i.MX31 and i.MX31L. The external low frequency clock (CKIL) can use either a 32 kHz, 32.768 kHz or a 38.4 kHz crystal as its source. For applications that require a high frequency clock source the CCM has a CKIH pin to which an external high frequency clock can be connected. The CCM provides a large number of clock outputs used to supply clocks to the MCU and the peripherals. The i.MX31 and i.MX31L are partitioned into two asynchronous clock domains: MCU and USB, as there are different functionality and frequency requirements from these clocks. The main clock of the MCU clock domain is mcu_main_clk and is generated by MCU clock switch unit. The MCU clock domain is partitioned into four synchronous clocks and two sub-domains. The main clock of this domain is called mcu_main_clk, and it is the output of the MCU clock switch unit. The main clock of the USB clock domain is usb_main_clk and is generated by the USB clock switch unit. Another part of the CCM is the low-power clock gating (LPCG). The LPCG block distributes clocks to all modules from the subdomain clocks and gates off clocks in low-power mode. Clock gating for each module is carried out based on the specific low-power mode and the relevant bits in the MCGR register. The power management portion of the i.MX31 and i.MX31L is controlled by the CCM. To this end, the i.MX31 and i.MX31L are partitioned into four power domains. The i.MX31 and i.MX31L support a versatile definition of power modes, including power and clock domains status and applied power techniques. The power modes are Run, Wait, Doze, State Retention, Deep Sleep, and Hibernate. The CCM supports several power management techniques that reduce active and static power consumption: * Dynamic Voltage Frequency Scaling (DVFS) reduces active power consumption by scaling voltage and frequency accordingly to required MIPs. i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 9 Functional Description and Application Information * * * * * Dynamic Process Temperature Compensation (DPTC) reduces active power consumption by adjusting supply voltage accordingly specific process cases, the manner in which the chip was fabricated, and the ambient temperature. State Retention Voltage (SRV) reduces static power consumption by decreasing supply voltage to minimum State Retention level. Chip is not functional in this mode. Active Well Bias (AWB) reduces static power consumption by applying back bias on transistors. AWB can be applied on ARM11P. ARM11P is not functional when AWB is applied. L2 Cache Power Gating--Reduces static power consumption by eliminating L2 Cache leakage. ARM11P Power Gating--Reduces static power consumption by eliminating ARM11P leakage. 2.3.5 Configurable Serial Peripheral Interface (CSPI) The CSPI is used for fast data communication with fewer software interrupts. There are three identical CSPI modules in the i.MX31 and i.MX31L that provide full-duplex synchronous serial interface. It is master/slave configurable and includes four chip selects to support multiple peripherals. In addition, the transfer continuation function of the CSPI allows unlimited length data transfers using 32-bit wide by 8 entry FIFO for both TX and RX data DMA support. The CSPI is equipped with data FIFOs and is a master/slave configurable serial peripheral interface module, capable of interfacing to both SPI master and slave devices. The CSPI Ready (SPI_RDY) and Chip Select (SS) control signals enable fast data communication with fewer software interrupts. When the CSPI module is configured as a master, it uses a serial link to transfer data between the CSPI and an external device. A chip-enable signal and a clock signal are used to transfer data between these two devices. When the CSPI module is configured as a slave, the user can configure the CSPI Control register to match the external SPI master's timing. 2.3.6 Embedded Cross Trigger (ECT) The ECT scheme is based on the ECT debugging hardware from ARM Ltd. The ECT is composed of three CTIs (Cross Trigger Interface) and one CTM (Cross Trigger Matrix). The ECT is key in the multi-core and multi-IP debug strategy. The outcome is a SW-controlled debug signal matrix that receives many signals from various sources (i.e. cores and peripherals) and propagates/routes them to the different debug resources of the SoC. As seen in previous sections, those debug resources can include profiling capabilities, real-time trace (trace enabled or disabled), triggers, SOC level multiplexing, and debug interrupts. The main advantages of using the ECT are that it provides a standardized debug scheme, in line with ARM RealView debugger, simplifies integration with ARM debug tools. Another advantage is that within a single debug domain, all the IPs can share the same debug resources and there is no need to duplicates counters or real-time trace resources. One trace port can be used with one tool to track the activity of the core and its peripherals. Since ECT should only be used during debug sessions, it is off (disabled) by default. i.MX31/i.MX31L Advance Information, Rev. 1.4 10 Preliminary Freescale Semiconductor Functional Description and Application Information 2.3.7 External Memory Interface (EMI) The EMI controls all memory accesses external to the i.MX31 and i.MX31L (read/write/erase/program) from all the masters in the system. This is done by using two port interfaces MPG (AHB 32 bit) and MPG64 (AHB 64 bit) toward different external memories. The EMI includes interface elements, and controllers of external memories, as shown in the list below: * M3IF--Multi Master Memory Interface. * ESDCTL/MDDRC--Enhanced SDRAM/MDDR memory controller. * PCMCIA--PCMCIA memory controller. * NFC--NAND Flash memory controller. * WEIM--SRAM/PSRAM/FLASH memory controller. All accesses via the EMI are arbitrated by the Multi Master Memory Interface (M3IF) and controlled by the respective memory controller. The M3IF - ESDCTL/MDDRC interface is designed to reduce access latency by generating multiple accesses through the dedicated ESDCTL/MDDRC arbitration (MAB) module, which controls the access towards/from the Enhanced SDRAM/MDDR memory controller. For the other memory interfaces (PCMCIA, NFC, WEIM), the M3IF only arbitrates and forwards the masters requests received through the Master Port Gasket (MPG/MPG64) interface. The M3IF - Multi Master Memory Interface controls memory accesses (read/write/erase/program) from one or more masters through different port interfaces toward different external memory controllers. The masters arrive from the ARM Platform, the SDMA, the MPEG-4 encoder, or the IPU. The controllers are: ESDCTL/MDDRC, PCMCIA, NANDFLASH and WEIM. The interface between the M3IF and the controllers can be divided into two different types: M3IF-ESDCTL, and M3IF-all others. For the other port interfaces, the M3IF arbitrates and forwards the masters' requests received through the Master Port Gasket (MPG) interfaces and the M3IF arbitration (M3A) module toward the respective memory controller. The Enhanced SDRAM Controller consists of 10 major blocks, including the SDRAM command state machine controller, bank register (page and bank address comparators), Row/Column Address Multiplexer & decoder, configuration registers, refresh request sequencer, command sequencer, size logic (splitting access), data path (data aligner/multiplexer), MDDR interface, and the Power Down timer. Since up to two SDRAMs can be connected to the ESDCTL, and each SDRAM has 4 banks, there are a total of 8 bank controllers. The bank controllers can also be used as comparators for timing parameters. The NAND Flash Controller (NFC) interfaces standard NAND Flash devices to the i.MX31 and i.MX31L and hides the complexities of accessing the NAND Flash. It provides a glueless interface to both 8-bits and 16-bits NAND Flash parts with page sizes of 512 Bytes or 2 Kilobytes. It addressing scheme allows it to accesses flash devices of almost limitless capacities. The 2 kilobyte RAM buffer of the NAND Flash is used as the boot RAM during a cold reset (if the i.MX31 and i.MX31L are configured for a boot to be carried out from the NAND Flash device). After the boot procedure completes, the RAM is available as buffer RAM. In addition, the NAND Flash controller provides an X16 bit and X32 bit interface to the AHB bus on the chip side, and an X8/X16 interface to the NAND Flash device on the external side. The Wireless External Interface Module (WEIM) handles the interface to devices external to chip, including generation of chip selects, clocks and controls for external peripherals and memory. It provides asynchronous and synchronous access to devices with SRAM-like interface.The WEIM includes six chip i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 11 Functional Description and Application Information selects for external devices, with two CS signals covering a range of 128Mbytes, and the other four each covering a range of 32Mbytes.The 128 Mbyte range can be increased to 256Mbytes when combined with combining the two signals. The WEIM offers selectable protection for each chip select as well as programmable data port size. There is a programmable wait-state generator for each chip select and support for Big Endian and Little Endian modes of operation per access. 2.3.8 Enhanced Periodic Interrupt Timer (EPIT) The EPIT is a 32-bit "set and forget" timer which starts counting after the EPIT is enabled by software and can generate an interrupt generation when counter reaches the Compare value. It is capable of providing precise interrupts at regular intervals with minimal processor intervention.The EPIT is based on a 32-bit down counter with selectable clock. It also has a 12-bit prescaler for division of input clock frequency. The counter value can be programmed on the fly and can also be programmed to be active in both low power and debug modes. 2.3.9 Fast InfraRed Interface (FIR) The Fast InfraRed Interface module (FIR) is capable of establishing a 0.576 Mbit/s, 1.152 Mbit/s or 4 Mbit/s half duplex link via a LED and IR detector. It supports 0.576 Mbit/s, 1.152 Mbit/s Medium InfraRed (MIR) physical layer protocol and 4Mbit/s Fast InfraRed (FIR) physical layer protocol defined by IrDA, version 1.4. In addition, the Serial InfraRed (SIR) protocol, which supports data rate 115.2kbps or lower, is implemented in UART module. The FIR interface signals are multiplexed with the UART counterpart signals via GPIO configuration for a complete InfraRed Interface supporting SIR, MIR and FIR modes. 2.3.10 General Purpose I/O Module (GPIO) The general-purpose input/output (GPIO) peripheral provides dedicated general-purpose pins that can be configured as either inputs or outputs. When configured as an output, you can write to an internal register to control the state driven on the output pin. When configured as an input, you can detect the state of the input by reading the state of an internal register. The GPIO includes all of the general purpose input/output logic necessary to drive a specific data to the pad and control the direction of the pad using registers in the GPIO module. The ARM11 is able to sample the status of the corresponding pads by reading the appropriate status register. The GPIO supports up to 32 interrupts and has the ability to identify interrupt edges as well as generate three active high interrupts. 2.3.11 General Purpose Timer (GPT) The General purpose timer (GPT) has a 32 bit up-counter. The timer counter value can be captured in a register using an event on an external pin. The capture trigger can be programmed to be a rising or/and falling edge. The GPT can also generate an event on ipp_do_cmpout pins and an interrupt when the timer reaches a programmed value. It has a 12-bit prescaler providing a programmable clock frequency derived from multiple clock sources. The GPT has one 32 bit up-counter with clock source selection, including external clock, two input capture channels with programmable trigger edge, and three output compare channels with programmable output mode. The GPT can perform a forced compare and can configured to i.MX31/i.MX31L Advance Information, Rev. 1.4 12 Preliminary Freescale Semiconductor Functional Description and Application Information be programmed to be active in low power and debug modes Interrupt generation can be programmed for capture, compare, rollover events and the timers offers both restart or free-run modes of operation. 2.3.12 Graphics Processing Unit (GPU) The GPU provides hardware acceleration for 2D and 3D graphics algorithms. The quality is sufficient for running desk-top quality interactive graphics applications on displays whose resolution is equivalent to VGA (and above) and whose color representation is up to 32 bits per pixel. The i.MX31 and i.MX31L's GPU is built around an ARM MBX R-S graphics accelerator. The GPU operates on 3D scene data (sent as batches of triangles) that are transformed and lit by the VGP. Triangles are written directly to the TA on a First In First Out (FIFO) basis so that the CPU is not stalled. In addition, the SDMA can be used to perform batch transfers with very low CPU involvement. The TA performs advanced culling on triangle data by writing the tiled non-culled triangles to the external memory. The event manager uses SmartBuffer technology for control. As a result, any level of scene complexity is handled in a fixed display list buffer size. The HSR engine reads the tiled data and implements per-pixel HSR with full Z-accuracy. The resulting visible pixels are textured and shaded in Internal True Color (ITC, 24 bit per pixel) before rendering the final image for display buffer. NOTE The GPU is not available on the i.MX31L. 2.3.13 Inter IC Communication (I2C) I2C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange, minimizing the interconnection between devices. This bus is suitable for applications requiring occasional communications over a short distance between many devices. The flexible I2C allows additional devices to be connected to the bus for expansion and system development. The I2C operates up to 400 kbps but it depends on the pad loading and timing (for pad requirement details please refer to Philips I2C Bus Specification, Version 2.1). The I2C system is a true multiple-master bus including arbitration and collision detection that prevents data corruption if multiple devices attempt to control the bus simultaneously. This feature supports complex applications with multiprocessor control and can be used for rapid testing and alignment of end products through external connections to an assembly-line computer. 2.3.14 IC Identification Module (IIM) The IIM provides an interface for reading and in some cases programming and/or overriding identification and control information stored in on-chip fuse elements. The module supports laser fuses (L-Fuses) or electrically-programmable poly fuses (e-Fuses) or both kinds. The IIM also provides a set of volatile software-accessible signals which can be used for software control of hardware elements, not requiring non-volatility. The IIM provides the primary user-visible mechanism for interfacing with on-chip fuse elements. Among the uses for the fuses are unique chip identifiers, mask revision numbers, cryptographic keys, and various control signals requiring permanent non-volatility. The IIM also provides up to 28 volatile control signals and a means to generate a second 168-bit SCC key. i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 13 Functional Description and Application Information The IIM consists of a master controller, a software fuse value shadow cache, and a set of registers to hold the values of signals visible outside the module. Up to eight arrays of fuses (L-Fuses and/or e-Fuses) are associated with the IIM, but are instantiated outside it. The IIM is accessible via an 8-bit IP bus interface. An 8-bit interface is used because it matches the natural width of the fuse arrays. All registers are 32-bit aligned, to allow the module to be instantiated on IP buses supporting only 32-bit peripherals. A subset of fuses, as well as the software-controlled volatile signals, are capable of driving top-level nets within the SoC. These signals are hereinafter referred to as Hardware-Visible Signals, or HW-Visible Signals. These signals are intended for feature enablement and disablement and similar uses within the device. Laser fuses can only be blown during chip manufacturing (at the wafer level). The e-Fuses may be blown under software or JTAG control during IC final test, at the customer factory or in the field. They include a mechanism to inhibit further blowing of fuses (write-protect), to support secure computing environments. The fuse values may also be overridden by software without modifying the fuse element. Similar to the write-protect functionality, the override functionality can also be permanently disabled. Fuse banks may also be scan-inhibited on a per-bank basis to prevent reading and programming of fuses through the JTAG interface. 2.3.15 Image Processing Unit (IPU) The IPU is designed to support video and graphics processing functions in the i.MX31 and i.MX31L and to interface to video/still image sensors and displays. The IPU can capture image data from a camera sensor or from a TV decoder. The captured image can be sent to preprocessing or stored in an external system memory for additional processing on the ARM11 platform. Preprocessing of data can be programmed from the sensor or from the external system memory. There are two preprocessing channels determined by the data destination - an encoder or a display (viewfinder mode). Preprocessing includes downsizing with independent integer horizontal and vertical ratios, resizing with independent fractional horizontal and vertical ratios, color space conversion, combining a video plane with a graphics plane (blending on graphics on top of video plane), Data postprocessing from the external system memory. The MCU can invoke a number of postprocessing channels sequentially by re-programming the IPU after finish of previous channel frame processing. Postprocessing includes downsizing with independent integer horizontal and vertical ratios, resizing with independent fractional horizontal and vertical ratios, color space conversion and combining a video plane with a graphics plane (blending on graphics on top of video plane). It also provides 90 degree rotation, up/down and left/right flipping of the image. Post-filtering of data from the system memory with support of the MPEG-4 (both deblocking and deringing) and H.264 post-filtering algorithms. The IPU provides for the display of video and graphics on a synchronous (dump or memoryless) display by displaying video and graphics on an asynchronous (smart) display. There are two mechanisms to support smart display or graphic accelerator functionality: interleaving data and commands from a command buffer prepared by the MCU or automatic commands generation according to a prepared template. The data can be sent to the smart display from the system memory, internal IPU processing modules or directly from the MCU or the system DMA controller. i.MX31/i.MX31L Advance Information, Rev. 1.4 14 Preliminary Freescale Semiconductor Functional Description and Application Information 2.3.16 Keypad Port (KPP) The Keypad Port is designed to interface with keypad matrix with 2-contact or 3-point contact keys. The Keypad Port is designed to simplify the software task of scanning a keypad matrix. With appropriate software support, the KPP is capable of detecting, debouncing and decoding one or multiple keys pressed simultaneously in the keypad. The KPP supports up to 8 x 8 external key pad matrix. Its port pins can be used as general purpose I/O. Using an open drain design the KPP includes glitch suppression circuit design, multiple keys, long key, and standby key detection. 2.3.17 MPEG-4 Video Encoder (MPEG-4) The MPEG-4 encoder in the i.MX31 and i.MX31L accelerates video compression, in compliance with the MPEG-4 standard. The encoder provides several levels of compression formats including MPEG-4 simple profile (all levels) and H.263 baseline. The encoder can encode at a pixel rate up to VGA @ 30 fps and compressed bit-rates up to 4 Mbps. The MPEG-4 encoder provides what is essentially the complete video processing chain, generating a Huffman-coded stream with the exception of the formation of the final MPEG-4 stream which is the only burden put on the ARM11 processor. Additional processing provided by the MPEG-4 encoder includes picture smoothening (low-pass filter) and camera movement stabilization. Support for enhanced conference call format in the form of additional information inserted within the MPEG stream, used by a MPEG-4 decoder to improve performance. 2.3.18 Memory Stick Host Controller (MSHC) The MSHC is located between the AIPS and the Sony Memory Stick and provides support for data transfers between the i.MX31/i.MX31L and the Memory Stick (MS). The memory stick host controller consists of two sub modules; the MSHC gasket and the Sony Memory Stick Host Controller (SMSC). The SMSC module, which is the actual memory stick host controller, is compatible with Sony Memory Stick Ver 1.x and Memory Stick PRO. The gasket connects the AIPS IP bus to the SMSC interface to allow communication and data transfers via the IP Bus. The MSHC gasket uses a reduced IP Bus interface that supports the IP bus read/write transfers that include a back-to-back read or write {mshc_rd_wr_data,back_to_back_rw, back_to_back_complex}. DMA transfers also take place via the IP Bus interface.{mshc_sdma}. A transfer can be initiated by the SDMA or the host (through AIPS) in response to an MSHC DMA request or interrupt. The SMSC has two SDMA address modes--a single address mode and a dual address mode. The MSHC is set to dual address mode for transfers with the SDMA. In dual address mode, when the MSHC requests a transfer with the DMA request (XDRQ), the SDMA will initiate a transfer to the MSHC. NOTE All details regarding the operation of the SMSC module can be found separately in "Memory Stick/Memory Stick PRO Host Controller IP Specification 1.3". i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 15 Functional Description and Application Information 2.3.19 PCMCIA Host Adapter (PCMCIA) The PCMCIA Host Adapter provides the control logic for PCMCIA socket interfaces, and requires some additional external analog power switching logic and buffering. The PCMCIA host adapter module is fully compliant with the PCMCIA standard release 2.1 (PC Card -16) and supports one PCMCIA socket. The adapter supports hot-insertion, card detection and removal, CompactFlash(R), and ATA emulation in TrueIDE mode. The PCMCIA maps to common memory space, attribute memory space and I/O space. Each space can be up to 64Mbyte in size. As part of the EMI complex the PCMCIA shares its pins with the WEIM, SDRAMC, and NFC. 2.3.20 Pulse-Width Accelerator (PWM) The PWM has a 16-bit counter and is optimized to generate sounds from stored sample audio images and it can also generate tones. It uses 16-bit resolution and a 4x16 data FIFO to generate sound. The following features characterize the PWM. the 16-bit up-counter has a source selectable clock with 4 x 16 FIFO to minimize interrupt overhead. Clock in frequency is controlled by a12-bit prescaler for division of clock. Capable of sound and melody generation the PWM has an active high or active low configurable output and can be programmed to be active in low power and debug modes. The PWM can be programmed to generate interrupts at compare and rollover events. 2.3.21 Random Number Generator Accelerator (RNGA) The RNGA module is a digital integrated circuit capable of generating 32-bit random numbers. The RNGA is designed to comply with FIPS-140 standards for randomness and non-determinism. The random bits are generated by clocking shift registers with clocks derived from ring oscillators. The configuration of the shift registers ensures statistically good data (that is, data that looks random). The oscillators with their unknown frequencies provide the required entropy needed to create random data. It is important to note that there is no known cryptographic proof showing that this is a secure method of generating random data. In fact, there may be an attack against the random number generator described in this document if its output is used directly in a cryptographic application (the attack is based on the linearity of the internal shift registers). Due to lack of a secure method and the potential for attacks, Freescale Semiconductor recommends that the random data produced by this module be used as an input seed to a NIST approved (based on DES or SHA-1) or cryptographically secure (RSA Generator or BBS Generator) random number generation algorithm. It is also recommended that other sources of entropy be used along with the RNGA to generate the seed to the pseudo-random algorithm. But this is optional. The more random sources combined to create the seed the better. The RNGA uses a 32-bit IP Bus slave interface and contains a 16 x 32 FIFO. It provides a Secure mode or operations as well as a power saving mode 2.3.22 Real Time Clock (RTC) The RTC module maintains the system clock, provides stopwatch, alarm, and interrupt functions, and supports the following features. * Full clock--days, hours, minutes, seconds i.MX31/i.MX31L Advance Information, Rev. 1.4 16 Preliminary Freescale Semiconductor Functional Description and Application Information * * * * * Minute countdown timer with interrupt Programmable daily alarm with interrupt Sampling timer with interrupt Once-per-day, once-per-hour, once-per-minute, and once-per-second interrupts Operation at 32.768 kHz, 32 kHz, or 38.4 kHz (determined by reference clock crystal) The prescaler converts the incoming crystal reference clock to a 1 Hz signal which is used to increment the seconds, minutes, hours, and days TOD counters. The alarm functions, when enabled, generate RTC interrupts when the TOD settings reach programmed values. The sampling timer generates fixed-frequency interrupts, and the minute stopwatch allows for efficient interrupts on very small boundaries. 2.3.23 Run-TIme Integrity Checker (RTIC) The RTIC is one of the security components in the i.MX31 and i.MX31L. Its purpose is to ensure the integrity of the peripheral memory contents and assist with boot authentication. The RTIC has the ability to verify the memory contents during system boot and during run-time execution. If the memory contents at runtime fail to match the hash signature, an error in the security monitor is triggered. The RTIC provides SHA-1 message authentication and receives input via the DMA (AMBA-AHB Lite bus master) interface. It uses segmented data gathering to support non-contiguous data blocks in memory (up to two segments per block) and works during and with High Assurance Boot (HAB) process. It provides Secure-scan DFT security and support for up to four independent memory blocks. The RTIC has both a programmable DMA bus duty cycle timer and its own watchdog timer. The RTIC operates in two primary modes: One time hash mode and continuous hash mode. The One time hash mode is used during HAB for code authentication or one time integrity checking during which it stores the hash result internally and signals the ARM11 using an interrupt. In Continuous hash mode the RTIC is used continuously to verify integrity of memory contents by checking re-generated hash against internally stored values and interrupts host only if error occurs. 2.3.24 Security Controller Module (SCC) Security and security services, in an embedded or data processing platform, refer to the i.MX31 and i.MX31L processor's ability to provide mandatory and optional information protection services. Information in this context refers to all embedded data, both program store and data load. Therefore, a secure platform is intended to protect information/data from unauthorized access in the form of inspection (read), modification (write) or execution (use). Security assurance refers to the degree of confidence that security claims are actually met and is therefore associated with the resources available to, and the integrity of, a given security design. The SCC is a hardware security component composed of two subblocks, the Secure RAM and the Security Monitor Overall its primary functionality is associated with establishing a centralized security state controller and hardware security state with a hardware configured, unalterable security policy. It also provides an uninterruptedly hardware mechanism to detect and respond to threat detection signals i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 17 Functional Description and Application Information (specifically platform test access signals). It also serves as a device unique data protection/encryption resource to enable off chip storage of security sensitive data and an internal storage resource which automatically and irrevocably destroys plain text security sensitive data upon threat detection. 2.3.25 Secure Digital Host Controller (SDHC) The MultiMediaCard (MMC), is a universal low cost data storage and communication media that is designed to cover a wide area of applications as electronic toys, organizers, PDAs and smart phones etc. The MMC communication is based on an advanced 7 pin serial bus designed to operate in a low voltage range. The Secure Digital Card (SD), is an evolution of MMC technology, with two additional pins in the form factor. It is specifically designed to meet the security, capacity, performance, and environment requirement inherent in newly emerging audio and video consumer electronic devices. The physical form factor, pin assignment and data transfer protocol are forward compatible with the MultiMediaCard with some additions. Under SD, it can be categorized into Memory and I/O. The memory card invokes a copyright protection mechanism that complies with the security of the SDMI standard. It will be faster and provide the capability for a higher memory capacity. The I/O card provides high-speed data I/O with low power consumption for mobile electronic devices. The SDHC controls the MMC, SD memory, and I/O cards by sending commands to cards and performing data accesses to/from the cards.The Multimedia Card/Secure Digital Host module (MMC/SD) integrates both MMC support along with SD memory and I/O functions. The SDHC is fully compatible with the MMC System Specification Version 3.0 as well as compatible with the SD Memory Card Specification 1.0, and SD I/O Specification 1.0 with 1/4 channel(s). The maximum data rate in 4-bit mode is 100 Mbps. The SDHC uses a built-in programmable frequency counter for SDHC bus and provides a maskable hardware interrupt for SDIO Interrupt, Internal status & FIFO status and it has a 32x16-bit data FIFO buffer built-in. 2.3.26 SDMA The SDMA architecture offers highly-competitive DMA Controller features combined with software-based virtual-DMA flexibility. Furthermore, it enables data transfers between peripheral I/O devices and internal/external memories. The Smart Direct Memory Access (SDMA) controller is a critical piece of hardware in a highly integrated IC like a 3G Baseband chip or a Multimedia SoC. It helps maximizing system performance by off-loading the CPU in dynamic data routing. It contains a custom RISC core along with its RAM, ROM, the three DMA units, the CRC unit, and the scheduler. The SDMA is used to execute short routines that perform DMA transfers; these routines or programs are called scripts hereafter. The Instruction-Set is composed of single cycle instructions with the exception of Load/Store instructions to the internal memory (RAM, ROM and memory mapped registers), to the registers of the DMA and CRC units, and Branch instructions that may require several cycles to execute. The SDMA core is interfaced to its own memory via the SDMA System Bus. The SDMA System Bus supports a 32-bit data path and a 16-bit address bus. DMA units are interfaced to the CORE via the Functional Unit Bus and use dedicated registers to perform DMA transfers. i.MX31/i.MX31L Advance Information, Rev. 1.4 18 Preliminary Freescale Semiconductor Functional Description and Application Information The SDMA memory is constituted of a ROM and a RAM. The ROM contains startup scripts (for example, boot code) and other common utilities which are referenced by the scripts that reside in the RAM. The internal RAM is divided into a context area and a script area. Every transfer channel requires one context area to keep the contents of all the CORE and units registers while it is inactive. Channel scripts are downloaded into the internal RAM by the SDMA using a dedicated channel that is started during the boot sequence. Downloads are invoked using command and pointers provided by the MCU or DSP. Every channel contains a corresponding channel script that is located in RAM and/or ROM; and it can be reconfigured independently on an "as needed" basis. This permits a wide range of SDMA functionality while using the lowest internal memory footprint possible. Channel scripts can be stored in an external, large capacity, FLASH memory and downloaded when needed. The SDMA can be configured with any mixture of scripts to enable an endless combination of supported services. The scheduler is responsible for monitoring and detecting DMA requests, mapping them to channels and mapping individual channels to a pre-configured priority. At any point in time, the scheduler will present the highest priority channel requiring service to the SDMA core. A special SDMA core instruction is used to "conditionally yield" the current channel being executed to an eligible channel that requires service. If, and only if, an eligible channel is pending will the current execution of a channel be pre-empted. There are two "yield" instructions that differently determine the eligible channels: in the first version, eligible channels are pending channels with a strictly higher priority than the current channel priority; in the second version ("yieldage"), eligible channels are pending channels with a priority that is greater or equal to the current channel priority. The scheduler detects devices needing service through its 32 DMA request inputs. After a request is detected, the scheduler determines the channel(s) that is (are) triggered by this request and marks it (them) as pending in the "Channel Pending (EP)" register. The priorities of all the pending channels are combined and continuously evaluated in order to update the highest pending priority. The channel pending flag is cleared by the channel script when the transfer has completed. The MCU Control module contains the control registers which are used to configure the 32 individual channels. There are 32 Channel Enable Registers: every register is used to map one DMA request to any desired combination of channels. The 32 Priority Registers are used to assign a programmable 1-of-7 level priority to every possible channel. This module also contains all other control registers that can be accessed by the MCU. The DSP Control module, when available, contains a restricted set of registers that enable the DSP to control the channels that have been allocated by the MCU approximately the same set of registers as the MCU Control module. The SDMA is either owned by the MCU or the DSP, never by both at the same time for security reasons. The master (MCU or DSP) that owns the SDMA is able to allocate channels to the other master; the latter that is not controlling the SDMA has a limited access to its control registers. The 32 DMA requests that are connected to the scheduler come from a variety of sources. The "receive register full" and "transmit register empty" signals that are found in UART and USB ports are typical examples of DMA requests that can be connected to the SDMA. These requests can be used to trigger a specific SDMA channel, or several channels. This feature can be used to realize a "just-in-time" data exchange between the two processors to relax the requirement to meet critical deadlines. The embedded nature of the SDMA requires on-chip debug capability to assure product quality and reliability and to realize the full performance capabilities of the core. The OnCE compatible debug port i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 19 Functional Description and Application Information includes support for setting breakpoints, Single-Step & Trace and register dump capability. In addition, all memory locations are accessible from the debug port. 2.3.27 Subscriber Identification Module (SIM) The SIM Interface Module (SIM) is designed to facilitate communication to SIM cards or Eurochip pre-paid phone cards. The SIM module has two ports that can be used to interface with the various cards. The interface with the MCU is via a 16-bit connection, The SIM module I/O interface can be operated in one of three modes of operation. Two wire interface. In this mode both the IC pin RX and IC pin TX are used to interface to the smartcard. This is activated by resetting the 3volt bit in the port control register to a "0". External one wire interface. In this mode the IC pins RX and TX are tied together external to the IC and routed to the smartcard. The 3volt bit in the port control register is reset to a "0" and the OD bit in the OD_CONFIG register is set to a "1". For this interface to work properly the IC pin (RX-TX) must be pulled high by a resistor. The value should be selected small enough to give a fast enough rise time. Internal one wire interface. In this mode the IC pin TX is routed to the smartcard. The receive pin RX is connected to the TX pin internal to the IC. The 3volt bit in the port control register is reset to a "1" and the OD bit in the OD_CONFIG register is set to a "1". For this interface to work properly the IC pin TX must be pulled high by a resistor. The value should be selected small enough to give a fast enough rise time. 2.3.28 Secure JTAG Controller (SJC) The IEEE1149.1 JTAG test access port (TAP) supports IEEE1149.1 v2001 standard features, access to OnCE and ICE of each Core, debug features to improve controllability and absorbability of the Cores for debug purposes, manufacturing test features (special test modes, PLL bypass, memory BIST and Burn-in...). The SJC provides debug and test control with the maximum security and provide a flexible architecture for future derivatives or future multi-cores architecture (how to add-remove a Core, software and hardware implications). JTAG pins can be muxed to the PCS bus connectors. The SJC operates at maximum 1/8 the slowest frequency of the accessed OnCE/ICE. For example in normal operation (no core in low-power mode), this frequency will be 1/8 of the SDMA frequency if this core is present in the TDI-TDO chain (serially connected with other cores or standalone). User needs also to take into account the 25MHz frequency limitation on the CE bus. In addition, secure JTAG options are provided to protect debug resources from attacks by unauthorized users. The secure JTAG design prevents the debug architecture from compromising security. 2.3.29 Synchronous Serial Interface (SSI) The SSI is a full-duplex, serial port that allows the chip to communicate with a variety of serial devices. These serial devices can be standard codecs, Digital Signal Processors (DSPs), microprocessors, peripherals, and popular industry audio codecs that implement the inter-IC sound bus standard (I2S) and Intel AC97 standard. i.MX31/i.MX31L Advance Information, Rev. 1.4 20 Preliminary Freescale Semiconductor Functional Description and Application Information SSI is typically used to transfer samples in a periodic manner. The SSI consists of independent transmitter and receiver sections with independent clock generation and frame synchronization. The SSI contains independent (asynchronous) or shared (synchronous) transmit and receive sections with separate or shared internal/external clocks and frame syncs, operating in Master or Slave mode. The SSI can work in normal mode operation using frame sync and in Network mode operation allowing multiple devices to share the port with as many as thirty-two time slots. The SSI provides 2 sets of Transmit and Receive FIFOs. Each of the four FIFOs is 8x24 bits. The two sets of Tx/Rx FIFOs can be used in Network mode to provide 2 independent channels for transmission and reception. It also has programmable data interface modes such like I2S, LSB, MSB aligned and programmable word lengths. Other program options include frame sync and clock generation and programmable I2S modes (Master, Slave or Normal). Oversampling clock, ccm_ssi_clk available as output from SRCK in I2S Master mode. In addition to AC97 support the SSI has completely separate clock and frame sync selections for the receive and transmit sections. In AC97 standard, the clock is taken from an external source and frame sync is generated internally. the SSI also has a programmable internal clock divider and Time Slot Mask Registers for reduced CPU overhead (for Tx and Rx both). 2.3.30 Universal Asynchronous Receiver/Transmitter (UART) The i.MX31 and i.MX31L contain five UART modules, Each UART module is capable of standard RS-232 non-return-to-zero (NRZ) encoding format and IrDA-compatible infrared modes. The UART provides serial communication capability with external devices through an RS-232 cable or through use of external circuitry that converts infrared signals to electrical signals (for reception) or transforms electrical signals to signals that drive an infrared LED (for transmission) to provide low speed IrDA compatibility. The UART transmits and receives characters containing either 7 or 8 bits (program selectable). To transmit, data is written from the IP data bus (Sky-Blue line interface) to a 32-byte transmitter FIFO (TxFIFO). This data is passed to the shift register and shifted serially out on the transmitter pin (TXD). To receive, data is received serially from the receiver pin (RXD) and stored in a 32-half-words-deep receiver FIFO (RxFIFO). The received data is retrieved from the RxFIFO on the IP data bus. The RxFIFO and TxFIFO generate maskable interrupts as well as DMA Requests when the data level in each of the FIFO reaches a programmed threshold level. The UART generates baud rates based on a dedicated input clock and its programmable divisor. The UART also contains programmable auto baud detection circuitry to receive 1 or 2 stop bits as well as odd, even, or no parity. The receiver detects framing errors, idle conditions, BREAK characters, parity errors, and overrun errors. 2.3.31 Universal Serial Bus (USB) The i.MX31 and i.MX31L provides three USB ports. The USB module provides high performance USB On-The-Go (OTG) functionality, compliant with the USB 2.0 specification, the OTG supplement and the ULPI 1.0 Low Pin Count specification. The module consists of 3 independent USB cores, each controlling 1 USB port. i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 21 Functional Description and Application Information In addition to the USB cores, the module provides for a Transceiverless Link (TLL) operation on host ports 1 and 2 and allows for routing the OTG transceiver interface to HOST port 1 such that this transceiver can be used to communicate with a USB peripheral connected to host port 1. The USB module has 2 connections to the CPU bus. One IP-bus connection for register accesses and one AHB-bus connection for DMA transfer of data to and from the FIFOs.The USB module includes the following features: * Full Speed / Low speed Host only core (HOST 1) * Transceiverless Link Logic (TLL) for on board connection to a FS/LS USB peripheral. * Bypass mode to route Host Port 1 signals to OTG I/O port * High Speed / Full Speed / Low Speed Host Only core (HOST2) * Full Speed / Low Speed interface for Serial transceiver. * TLL function for direct connection to USB peripheral in FS/LS (serial) operation * High speed OTG core The USB module has 2 main modes of operation; Normal mode and Bypass mode. Furthermore, the USB interfaces can be configured for High Speed operation (480 Mbps) and/or Full/Low speed operation (12/1.5 Mbps). In normal mode, each USB core controls its corresponding PORT. Each port can work in 1 or more modes PHY mode: In this mode, an external serial transceiver is connected to the port. This is used for off-board USB connections. TLL mode: In TLL mode, internal logic is enabled to emulate the functionality of 2 back-to-back connected transceivers. This mode is typically used for on-board USB connections to USB-capable peripherals. Host Port 2 supports ULPI and Serial Transceivers. The OTG port requires a transceiver and is intended for off-board USB connections. Serial Interface mode-In serial mode, a serial OTG transceiver must be connected. The port does not support dedicated signals for OTG signaling. Instead, a transceiver with built-in OTG registers must be used. Typically, the Transceiver registers are accessible over an I2C or SPI interface. ULPI Mode-It this mode, a ULPI transceiver is connected to the port pins to support High-speed off board USB connections. ULPI mode is activated by writing the following: Bypass mode-Bypass mode affects the operation of the OTG port and HOST port 1. This mode is only available when a serial transceiver is used on the OTG port, and the peripheral device on port 1 is using a TLL connection. Bypass mode is activated by setting the bypass bit in the USBCONTROL register. In this mode, the USB OTG port connections are internally routed to the USB HOST 1 port, such that the transceiver on the OTG port connects to a peripheral USB device on HOST port 1. The OTG core and the HOST 1 core are disconnected from their ports when bypass is active. Low Power mode-Each of the 3 USB cores has an associated power control module that is controlled by the USB core and clocked on a 32 kHz clock. When a USB bus is idle, the tranceiver can be placed in low power mode (suspend), after which the clocks to the USB core can be stopped. The 32 kHz low power clock must remain active as it is needed for wakeup detection. i.MX31/i.MX31L Advance Information, Rev. 1.4 22 Preliminary Freescale Semiconductor Signal Descriptions 2.3.32 Watchdog Module (WDOG) The Watchdog (WDOG) timer module protects against system failures by providing a method of escaping from unexpected events or programming errors. Once the WDOG module is activated, it must be serviced by software on a periodic basis. If servicing does not take place, the timer times out. Upon a time-out, the WDOG Timer module either asserts the wdog signal or a system reset signal wdog_rst depending on software configuration. The WDOG Timer module also generates a system reset via a software write to the Watchdog Control Register (WCR), a detection of a clock monitor event, an external reset, an external JTAG reset signal, or if a power-on-reset has occurred. 3 Signal Descriptions This section: * Identifies and defines all device signals in text, tables, and (as appropriate) figures. Signals can be organized by group, as applicable. * Contains pin-assignment/contact-connection diagrams, if the sequence of information in the data sheet requires them to be included here. Otherwise, these figures appear in Section 5, "Package Information and Pinout." 3.1 i.MX31 and i.MX31L I/O Pad Signal Settings This section identifies and defines all device signals in Table 4 on page 23, Table 6 on page 39, and Table 7 on page 56. 3.1.1 Functional Multiplexing Table 4 shows functional multiplexing information. Functional multiplexing allows the user to select the function of each pin by configuring the appropriate GPIO registers when those pins are multiplexed to provide different functions. Table 4. Functional Multiplexing Pin Name Group CAPTURE Timer Description Timer input Capture or Timer1 input clock. GPIO user for Memstick1 Card detect HW Hardware Mode Mode 1 2 ATA_DATA14 - SW_ MUX_ EN sw_mux_ctl_ capture [6:0] sw_mux_ctl_ compare [6:0] sw_mux_ctl_ watchdog_rs t[6:0] Alt Alt Alt Alt Alt Alt Mode Mode Mode Mode Mode Mode GPIO 1 2 3 4 5 6 - CMP2 - - - - MCU1_ 7 COMPARE Timer Timer Output Compare for ATA_DATA15 timers 1 2 3. GPIO used for Memstick2 card detect watchdog reset. - - CAP2 CMP3 - ipp_epit ipp_epit o1 o2 - - - MCU1_ 8 - WATCHDOG _RST PWMO GPIO1_0 WTDG - - IPU_FL ASH_S TROBE - - - - PWM GPIO1 PWM output. GPIO reserved for IRQs ATA_IORDY - - - sw_mux_ctl_ PC_SP pwmo[6:0] KOUT sw_mux_ctl_ EXTDM gpio1_0 A_0 [6:0] - - - - - - - - MCU1_ 9 MCU1_ 0 i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 23 Signal Descriptions Table 4. Functional Multiplexing (continued) Pin Name Group GPIO1_1 GPIO1 Description GPIO reserved for IRQs & DMA events GPIO reserved for IRQs & DMA events GPIO reserved for IRQs HW Hardware Mode Mode 1 2 - - SW_ MUX_ EN Alt Alt Alt Alt Alt Alt Mode Mode Mode Mode Mode Mode GPIO 1 2 3 4 5 6 - - - - - MCU1_ 1 MCU1_ 2 MCU1_ 3 MCU1_ 4 MCU1_ 5 MCU1_ 6 MCU3_ 0 MCU3_ 1 MCU3_ 2 MCU3_ 3 MCU2_ 0 MCU2_ 1 MCU2_ 2 MCU2_ 3 - sw_mux_ctl_ EXTDM gpio1_1 A_1 [6:0] sw_mux_ctl_ EXTDM gpio1_2 A_2 [6:0] sw_mux_ctl_ gpio1_3 [6:0] - GPIO1_2 GPIO1 - - - - - - - GPIO1_3 GPIO1 - - - - - - - GPIO1_4 GPIO1 GPIO used by USBH1 - - sw_mux_ctl_ USBH1 gpio1_4 _SUSP [6:0] END sw_mux_ctl_ gpio1_5 [6:0] sw_mux_ctl_ gpio1_6 [6:0] sw_mux_ctl_ gpio3_0 [6:0] sw_mux_ctl_ gpio3_1 [6:0] - - - - - - GPIO1_5 GPIO1 GPIO reserved for PMIC IRQ - - - - - - - GPIO1_6 GPIO1 GPIO reserved for Tamper TAMPER_DE detect TECT GPIO used as IPU CSI chip select3 GPIO used as IPU CSI chip select4 SIM Port 0 SPLL_BYPA SS_CLK UPLL_BYPA SS_CLK - - - - - - - - GPIO3_0 GPIO3 - - - - - - - GPIO3_1 GPIO3 - - - - - - - SCLK0 SIM - sw_mux_ctl_ CTI_TRI DISPB_ obs_int_ sclk0[6:0] G_IN_1 D2_CS 0 _4 sw_mux_ctl_ srst0[6:0] - DISPB_ obs_int_ D12_VS 1 YNC - obs_int_ 2 obs_int_ 3 obs_int_ 4 - - - - SRST0 SIM SIM Port 0 - - - - - SVEN0 SIM SIM Port 0 - - sw_mux_ctl_ CTI_TRI sven0[6:0] G_IN_1 _6 sw_mux_ctl_ CTI_TRI stx0[6:0] G_IN_1 _5 sw_mux_ctl_ srx0[6:0] sw_mux_ctl_ simpd0 [6:0] - - - - - - STX0 SIM SIM Port 0 - - - - - - SRX0 SIMPD0 SIM SIM SIM Port 0 SIM Port 0 - - - - - - - - - - - - CKIH Clock & Reset& PM Clock & Reset& PM Clock & Reset& PM Clock & Reset& PM Clock & Reset& PM Clock & Reset& PM 13-20 MHz clk input Osc input Master Reset from external power mgt chip No MUX allowed Power On Reset - - - - - - - - RESET_IN RESET_IN - sw_mux_ctl_ reset_in_b [6:0] - - - - - - - - POR - - - - - - - - - CLKO Clock out signal - - - - - - - - - - BOOT_MODE 0 BOOT_MODE 1 Boot Mode 0 - - - - - - - - - - Boot Mode 1 - - - - - - - - - - i.MX31/i.MX31L Advance Information, Rev. 1.4 24 Preliminary Freescale Semiconductor Signal Descriptions Table 4. Functional Multiplexing (continued) Pin Name Group BOOT_MODE 2 BOOT_MODE 3 BOOT_MODE 4 CKIL Clock & Reset& PM Clock & Reset& PM Clock & Reset& PM Clock & Reset& PM Clock & Reset& PM Clock & Reset& PM Clock & Reset& PM Clock & Reset& PM Clock & Reset& PM Clock & Reset& PM EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI Description Boot Mode 2 HW Hardware Mode Mode 1 2 - - SW_ MUX_ EN - Alt Alt Alt Alt Alt Alt Mode Mode Mode Mode Mode Mode GPIO 1 2 3 4 5 6 - - - - - - - Boot Mode 3 - - - - - - - - - - Boot Mode 4 - - - - - - - - - - 32 kHz clk input - - - - - - - - - - POWER_FAIL power shut-off input - - - - - - - - - - VSTBY Power management State retention Power management voltage change Power management voltage change Power management power gating Power management power gating EIM address 0 EIM address 1 EIM address 2 EIM address 3 EIM address 4 EIM address 5 EIM address 6 EIM address 7 EIM address 8 EIM address 9 EIM address 10 - EIM address 11 EIM address 12 - - sw_mux_ctl_ vstby[6:0] sw_mux_ctl_ dvfs0[6:0] sw_mux_ctl_ dvfs1[6:0] sw_mux_ctl_ vpg0[6:0] sw_mux_ctl_ vpg1[6:0] sw_mux_ctl_ a0[6:0] sw_mux_ctl_ a1[6:0] sw_mux_ctl_ a2[6:0] sw_mux_ctl_ a3[6:0] sw_mux_ctl_ a4[6:0] sw_mux_ctl_ a5[6:0] sw_mux_ctl_ a6[6:0] sw_mux_ctl_ a7[6:0] sw_mux_ctl_ a8[6:0] sw_mux_ctl_ a9[6:0] sw_mux_ctl_ a10[6:0] sw_mux_ctl_ ma10[6:0] sw_mux_ctl_ a11[6:0] sw_mux_ctl_ a12[6:0] - - - - - - - DVFS0 - - - - - - - - - DVFS1 - - - - - - - - - VPG0 - - - - - - - - - VPG1 - - - - - - - - - A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 MA10 A11 A12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 25 Signal Descriptions Table 4. Functional Multiplexing (continued) Pin Name Group A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 SDBA1 SDBA0 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 SD16 SD17 SD18 SD19 SD20 SD21 SD22 EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI Description EIM address 13 EIM address 14 EIM address 15 EIM address 16 EIM address 17 EIM address 18 EIM address 19 EIM address 20 EIM address 21 EIM address 22 EIM address 23 EIM address 24 EIM address 25 EIM Bank Address EIM Bank Address DDR/SDRAM Data 0 DDR/SDRAM Data 1 DDR/SDRAM Data 2 DDR/SDRAM Data 3 DDR/SDRAM Data 4 DDR/SDRAM Data 5 DDR/SDRAM Data 6 DDR/SDRAM Data 7 DDR/SDRAM Data 8 DDR/SDRAM Data 9 DDR/SDRAM Data 10 DDR/SDRAM Data 11 DDR/SDRAM Data 12 DDR/SDRAM Data 13 DDR/SDRAM Data 14 DDR/SDRAM Data 15 DDR/SDRAM Data 16 DDR/SDRAM Data 17 DDR/SDRAM Data 18 DDR/SDRAM Data 19 DDR/SDRAM Data 20 DDR/SDRAM Data 21 DDR/SDRAM Data 22 HW Hardware Mode Mode 1 2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SW_ MUX_ EN sw_mux_ctl_ a13[6:0] sw_mux_ctl_ a14[6:0] sw_mux_ctl_ a15[6:0] sw_mux_ctl_ a16[6:0] sw_mux_ctl_ a17[6:0] sw_mux_ctl_ a18[6:0] sw_mux_ctl_ a19[6:0] sw_mux_ctl_ a20[6:0] sw_mux_ctl_ a21[6:0] sw_mux_ctl_ a22[6:0] sw_mux_ctl_ a23[6:0] sw_mux_ctl_ a24[6:0] sw_mux_ctl_ a25[6:0] sw_mux_ctl_ sdba1[6:0] sw_mux_ctl_ sdba0[6:0] - - - - - - - - - - - - - - - - - - - - - - - Alt Alt Alt Alt Alt Alt Mode Mode Mode Mode Mode Mode GPIO 1 2 3 4 5 6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - i.MX31/i.MX31L Advance Information, Rev. 1.4 26 Preliminary Freescale Semiconductor Signal Descriptions Table 4. Functional Multiplexing (continued) Pin Name Group SD23 SD24 SD25 SD26 SD27 SD28 SD29 SD30 SD31 DQM0 DQM1 DQM2 DQM3 EB0 EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI Description DDR/SDRAM Data 23 DDR/SDRAM Data 24 DDR/SDRAM Data 25 DDR/SDRAM Data 26 DDR/SDRAM Data 27 DDR/SDRAM Data 28 DDR/SDRAM Data 29 DDR/SDRAM Data 30 DDR/SDRAM Data 31 Byte strobe DDR data enable Byte strobe DDR data enable Byte strobe DDR data enable Byte strobe DDR data enable LSB Byte strobe WEIM data enable; Controls D[7:0] LSB Byte strobe WEIM data enable Controls D[15:8] Memory Output enable Chip select 0 Chip select 1 Chip select 2/ SDRAM Sync Flash chip select Chip select 3/ SDRAM Sync Flash chip select Chip select 4 Chip select 5 End Current Burst Load Base Address used by Flash for burst mode read/write signal or WE for external DRAM SDRAM row address select SDRAM column address select SDRAM write enable SDRAM clock enable0 SDRAM clock enable1 SDRAM clock DDR clock pad HW Hardware Mode Mode 1 2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SW_ MUX_ EN - - - - - - - - - sw_mux_ctl_ dqm0[6:0] sw_mux_ctl_ dqm1[6:0] sw_mux_ctl_ dqm2[6:0] sw_mux_ctl_ dqm3[6:0] sw_mux_ctl_ eb0[6:0] sw_mux_ctl_ eb1[6:0] sw_mux_ctl_ oe[6:0] sw_mux_ctl_ cs0[6:0] sw_mux_ctl_ cs1[6:0] sw_mux_ctl_ cs2[6:0] sw_mux_ctl_ cs3[6:0] sw_mux_ctl_ cs4[6:0] sw_mux_ctl_ cs5[6:0] - sw_mux_ctl_ lba[6:0] sw_mux_ctl_ bclk[6:0] sw_mux_ctl_ rw[6:0] sw_mux_ctl_ ras[6:0] sw_mux_ctl_ cas[6:0] sw_mux_ctl_ sdwe[6:0] sw_mux_ctl_ sdcke0[6:0] sw_mux_ctl_ sdcke1[6:0] sw_mux_ctl_ sdclk[6:0] Alt Alt Alt Alt Alt Alt Mode Mode Mode Mode Mode Mode GPIO 1 2 3 4 5 6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - EB1 EMI - - - - - - - - - OE CS0 CS1 CS2 CS3 CS4 CS5 ECB LBA BCLK RW RAS CAS SDWE SDCKE0 SDCKE1 SDCLK EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 27 Signal Descriptions Table 4. Functional Multiplexing (continued) Pin Name Group SDCLK SDQS0 SDQS1 SDQS2 SDQS3 NFWE NFRE DDR EMI EMI EMI EMI EMI EMI Description False pad DDR_CLK DDR sample strobe DDR sample strobe DDR sample strobe DDR sample strobe NANDF NANDF HW Hardware Mode Mode 1 2 - - - - - ATA_DATA7 ATA_DATA8 - - - - - SW_ MUX_ EN - - - - - Alt Alt Alt Alt Alt Alt Mode Mode Mode Mode Mode Mode GPIO 1 2 3 4 5 6 - - - - - - - - - - - - USBH2 _DATA2 USBH2 _DATA3 USBH2 _DATA4 USBH2 _DATA5 USBH2 _DATA6 USBH2 _DATA7 - - - - - - - - - - - - - - - - - MSHC2 _SCLK - - - - - - - - - - - - TRACE DATA_0 TRACE DATA_1 TRACE DATA_2 TRACE DATA_3 TRACE DATA_4 TRACE DATA_5 TRACE DATA_6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - MCU1_ 10 MCU1_ 11 MCU1_ 12 MCU1_ 13 MCU1_ 14 MCU1_ 15 MCU1_ 16 - - - - - - - - - - - - - - - - - ATA_IN sw_mux_ctl_ TRQ nfwe_b[6:0] ATA_BU sw_mux_ctl_ FFER_E nfre_b[6:0] N ATA_DM sw_mux_ctl_ ARQ nfale[6:0] NFALE NFCLE NFWP NFCE NFRB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PC_CD1 EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI NANDF NANDF NANDF NANDF NANDF PCMCIA/WEIM/NANDF Data PCMCIA/WEIM/NANDF Data PCMCIA/WEIM/NANDF Data PCMCIA/WEIM/NANDF Data PCMCIA/WEIM/NANDF Data PCMCIA/WEIM/NANDF Data PCMCIA/WEIM/NANDF Data PCMCIA/WEIM/NANDF Data PCMCIA/WEIM/NANDF Data PCMCIA/WEIM/NANDF Data PCMCIA/WEIM/NANDF Data PCMCIA/WEIM/NANDF Data PCMCIA/WEIM/NANDF Data PCMCIA/WEIM/NANDF Data PCMCIA/WEIM/NANDF Data PCMCIA/WEIM/NANDF Data PCMCIA ATA_DATA9 - - NFWP - - - - - - - - - - - - - - - - - - SD2_ CMD - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ATA_DATA10 ATA_DA sw_mux_ctl_ 0 nfcle[6:0] ATA_DATA11 ATA_DA sw_mux_ctl_ 1 nfwp_b[6:0] ATA_DATA12 ATA_DA sw_mux_ctl_ 2 nfce_b[6:0] ATA_DATA13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - sw_mux_ctl_ nfrb[6:0] - - - - - - - - - - - - - - - - sw_mux_ctl_ pc_cd1_b [6:0] i.MX31/i.MX31L Advance Information, Rev. 1.4 28 Preliminary Freescale Semiconductor Signal Descriptions Table 4. Functional Multiplexing (continued) Pin Name Group PC_CD2 EMI Description PCMCIA HW Hardware Mode Mode 1 2 - - SW_ MUX_ EN Alt Alt Alt Alt Alt Alt Mode Mode Mode Mode Mode Mode GPIO 1 2 3 4 5 6 - - - - - sw_mux_ctl_ SD2_CL MSHC2 pc_cd2_b[6: K _BS 0] sw_mux_ctl_ SD2_DA MSHC2 pc_wait_b[6: TA0 _SDIO_ 0] DATA0 sw_mux_ctl_ SD2_DA MSHC2 pc_ready[6:0 TA1 _DATA1 ] sw_mux_ctl_ SD2_DA MSHC2 pc_pwron[6: TA3 _DATA2 0] sw_mux_ctl_ SD2_DA MSHC2 pc_vs1[6:0] TA2 _DATA3 sw_mux_ctl_ USBH2 UART5_ pc_vs2[6:0] _DATA2 RTS sw_mux_ctl_ USBH2 UART5_ pc_bvd1[6:0] _DATA3 RXD sw_mux_ctl_ USBH2 UART5_ pc_bvd2[6:0] _DATA4 TXD sw_mux_ctl_ USBH2 UART5_ pc_rst[6:0] _DATA5 CTS sw_mux_ctl_ USBH2 iois16[6:0] _DATA6 sw_mux_ctl_ USBH2 pc_rw_b[6:0] _DATA7 sw_mux_ctl_ pc_poe[6:0] - - sw_mux_ctl_ csi_d4[6:0] sw_mux_ctl_ csi_d5[6:0] sw_mux_ctl_ csi_d6[6:0] sw_mux_ctl_ csi_d7[6:0] sw_mux_ctl_ csi_d8[6:0] sw_mux_ctl_ csi_d9[6:0] sw_mux_ctl_ csi_d10[6:0] sw_mux_ctl_ csi_d11[6:0] sw_mux_ctl_ csi_d12[6:0] sw_mux_ctl_ csi_d13[6:0] sw_mux_ctl_ csi_d14[6:0] sw_mux_ctl_ csi_d15[6:0] - - - - - - - - - - PC_WAIT EMI PCMCIA - - - - - - - PC_READY EMI PCMCIA - - - - - - - PC_PWRON EMI PCMCIA - - - - - - - PC_VS1 PC_VS2 PC_BVD1 PC_BVD2 PC_RST IOIS16 PC_RW PC_POE M_REQUEST M_GRANT CSI_D4 EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI IPU (CSI) PCMCIA PCMCIA PCMCIA PCMCIA PCMCIA PCMCIA PCMCIA PCMCIA EMI sharing EMI sharing GPIO used as IPU CSI chip select1 GPIO used as IPU CSI chip select2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CTI_TRI MCU3_ G_OUT 4 _1_2 CTI_TRI MCU3_ G_OUT 5 _1_3 CTI_TRI MCU3_ G_OUT 6 _1_4 CTI_TRI MCU3_ G_OUT 7 _1_5 - - - - - - - - MCU3_ 8 MCU3_ 9 MCU3_ 10 MCU3_ 11 MCU3_ 12 MCU3_ 13 MCU3_ 14 MCU3_ 15 CSI_D5 IPU (CSI) - - - - - - - CSI_D6 IPU (CSI) Sensor Port Data 0 (bit 6) ATA_DATA0 - - - - - - CSI_D7 IPU (CSI) Sensor Port Data 1 (bit 7) ATA_DATA1 - - - - - - CSI_D8 CSI_D9 CSI_D10 CSI_D11 CSI_D12 CSI_D13 CSI_D14 CSI_D15 IPU (CSI) Sensor Port Data 2 (bit 8) IPU (CSI) Sensor Port Data 3 (bit 9) IPU (CSI) Sensor Port Data 4 (bit 10) IPU (CSI) Sensor Port Data 5 (bit 11) IPU (CSI) Sensor Port Data 6 (bit 12) IPU (CSI) Sensor Port Data 7 (bit 13) IPU (CSI) Sensor Port Data 8 (bit 14) IPU (CSI) Sensor Port Data 9 (bit 15) ATA_DATA2 ATA_DATA3 ATA_DATA4 ATA_DATA5 ATA_DATA6 ATA_DATA7 ATA_DATA8 ATA_DATA9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 29 Signal Descriptions Table 4. Functional Multiplexing (continued) Pin Name Group CSI_MCLK CSI_VSYNC Description HW Hardware Mode Mode 1 2 - - SW_ MUX_ EN sw_mux_ctl_ csi_mclk[6:0] sw_mux_ctl_ csi_vsync[6: 0] sw_mux_ctl_ csi_hsync[6: 0] sw_mux_ctl_ csi_pixclk[6: 0] sw_mux_ctl_ i2c_clk[6:0] - Alt Alt Alt Alt Alt Alt Mode Mode Mode Mode Mode Mode GPIO 1 2 3 4 5 6 - - - - - - - - - - - - MCU3_ 16 MCU3_ 17 MCU3_ 18 MCU3_ 19 - - IPU (CSI) Sensor Port master Clock ATA_DATA10 IPU (CSI) Sensor port vertical sync ATA_DATA11 CSI_HSYNC IPU (CSI) Sensor port horizontal Sync Sensor port data latch clock I2C clock I2C data TxD ATA_DATA12 - - - - - - - CSI_PIXCLK IPU (CSI) ATA_DATA13 - - - - - - - I2C_CLK I2C_DAT STXD3 I2C I2C AudioPort 3-BB (HP3) AudioPort 3-BB (HP3) AudioPort 3-BB (HP3) AudioPort 3-BB (HP3) AudioPort 4-PM_NB (PP1) AudioPort 4-PM_NB (PP1) AudioPort 4-PM_NB (PP1) AudioPort 4-PM_NB (PP1) AudioPort 5-PM_W B (PP2) AudioPort 5-PM_W B (PP2) AudioPort 5-PM_W B (PP2) AudioPort 5-PM_W B (PP2) AudioPort 6-BT (PP3) AudioPort 6-BT (PP3) ATA_DATA14 ATA_DATA15 ATA_DATA7 - - - - - - - - IPU_DI AGB[0] IPU_DI AGB[1] IPU_DI AGB[2] IPU_DI AGB[3] IPU_DI AGB[4] IPU_DI AGB[5] IPU_DI AGB[6] IPU_DI AGB[7] IPU_DI AGB[8] IPU_DI AGB[9] IPU_DI AGB[10] IPU_DI AGB[11] IPU_DI AGB[12] IPU_DI AGB[13] - - TRACE DATA_7 TRACE DATA_8 TRACE DATA_9 TRACE DATA_ 10 - - - - - USBH2 sw_mux_ctl_ _DATA2 stxd3[6:0] USBH2 sw_mux_ctl_ _DATA3 srxd3[6:0] USBH2 sw_mux_ctl_ _DATA4 sck3[6:0] USBH2 sw_mux_ctl_ _DATA5 sfs3[6:0] - EVNTB EMI_DE MCU1_ US_0 BUG0 17 EVNTB EMI_DE MCU1_ US_1 BUG1 18 EVNTB EMI_DE US_2 BUG2 EVNTB EMI_DE US_3 BUG3 - SRXD3 RxD ATA_DATA8 - - SCK3 Tx Serial Clock ATA_DATA9 - - SFS3 Tx Frame Sync ATA_DATA10 - - - STXD4 TxD - sw_mux_ctl_ RXFS3 stxd4[6:0] sw_mux_ctl_ RXCLK srxd4[6:0] 3 sw_mux_ctl_ RXFS5 sck4[6:0] sw_mux_ctl_ RXCLK sfs4[6:0] 5 sw_mux_ctl_ stxd5[6:0] sw_mux_ctl_ srxd5[6:0] sw_mux_ctl_ sck5[6:0] sw_mux_ctl_ sfs5[6:0] - - EVNTB EMI_DE MCU1_ US_4 BUG4 19 EVNTB ARM_C MCU1_ US_5 OREASI 20 D0 EVNTB ARM_C US_6 OREASI D1 EVNTB ARM_C US_7 OREASI D2 - SRXD4 RxD - - - - SCK4 Tx Serial Clock - - - - SFS4 Tx Frame Sync - - - - - STXD5 TxD - - - - EVNTB ARM_C MCU1_ US_8 OREASI 21 D3 EVNTB ARM_C MCU1_ US_9 OREASI 22 D4 EVNTB ARM_C US_10 OREASI D5 EVNTB ARM_C US_11 OREASI D6 - SRXD5 RxD - - - - - SCK5 Tx Serial Clock - - - - - SFS5 Tx Frame Sync - - - - - - STXD6 TxD ATA_DATA11 USBH2 sw_mux_ctl_ _DATA6 stxd6[6:0] USBH2 sw_mux_ctl_ _DATA7 srxd6[6:0] - - IPU_DI TRACE AGB[14] DATA_ 11 IPU_DI TRACE AGB[15] DATA_ 12 EVNTB ARM_C MCU1_ US_12 OREASI 23 D7 EVNTB M3IF_C MCU1_ US_13 HOSEN 24 _MAST ER_0 SRXD6 RxD ATA_DATA12 - - i.MX31/i.MX31L Advance Information, Rev. 1.4 30 Preliminary Freescale Semiconductor Signal Descriptions Table 4. Functional Multiplexing (continued) Pin Name Group SCK6 AudioPort 6-BT (PP3) AudioPort 6-BT (PP3) CSPI1_ BB CSPI1_ BB CSPI1_ BB CSPI1_ BB CSPI1_ BB CSPI1_ BB CSPI1_ BB CSPI2_ PM CSPI2_ PM CSPI2_ PM CSPI2_ PM CSPI2_ PM CSPI2_ PM CSPI2_ PM UART1_ GPS UART1_ GPS UART1_ GPS Description Tx Serial Clock HW Hardware Mode Mode 1 2 ATA_DATA13 - SW_ MUX_ EN sw_mux_ctl_ sck6[6:0] Alt Alt Alt Alt Alt Alt Mode Mode Mode Mode Mode Mode GPIO 1 2 3 4 5 6 - - IPU_DI TRACE AGB[16] DATA_ 13 IPU_DI TRACE AGB[17] DATA_ 14 IPU_DI TRACE AGB[18] DATA_ 15 IPU_DI TRACE AGB[19] DATA_ 16 EVNTB M3IF_C MCU1_ US_14 HOSEN 25 _MAST ER_1 EVNTB M3IF_C MCU1_ US_15 HOSEN 26 _MAST ER_2 - - - SFS6 Tx Frame Sync USBH1_SUS PEND - sw_mux_ctl_ sfs6[6:0] - - CSPI1_MOSI Master Out/Slave In. ATA_DATA0 ATA_IN sw_mux_ctl_ USBH1 TRQ cspi1_mosi[6 _RXDM :0] ATA_BU sw_mux_ctl_ USBH1 FFER_E cspi1_miso[6 _RXDP N :0] ATA_DM sw_mux_ctl_ USBH1 ARQ cspi1_ss0[6: _TXDM 0] ATA_DA sw_mux_ctl_ USBH1 0 cspi1_ss1[6: _TXDP 0] ATA_DA sw_mux_ctl_ USBH1 1 cspi1_ss2[6: _RCV 0] ATA_DA sw_mux_ctl_ USBH1 2 cspi1_sclk[6: _OEB 0] - sw_mux_ctl_ USBH1 cspi1_spi_rd _FS y[6:0] sw_mux_ctl_ I2C2_S cspi2_mosi CL [6:0] sw_mux_ctl_ I2C2_S cspi2_miso DA [6:0] sw_mux_ctl_ CSPI3_ cspi2_ss0 SS0 [6:0] RXD3 CSPI1_MISO Slave In/Master Out. ATA_DATA1 TXD3 - - - CSPI1_SS0 Slave Select (Selectable polarity). Slave Select (Selectable polarity). Slave Select (Selectable polarity). Serial Clock. ATA_DATA2 CSPI3_ IPU_DI TRACE SS2 AGB[20] DATA_ 17 CSPI2_ IPU_DI TRACE AGB[21] DATA_ SS3 18 CSPI3_ IPU_DI TRACE SS3 AGB[22] DATA_ 19 RTS3 IPU_DI AGB[23] IPU_DI AGB[24] - - - - - CSPI1_SS1 ATA_DATA3 - - - CSPI1_SS2 ATA_DATA4 - - - CSPI1_SCLK ATA_DATA5 - - - CSPI1_SPI_ RDY CSPI2_MOSI Serial Data Ready. ATA_DATA6 CTS3 - - - - Master Out/Slave In. - - - - - - - CSPI2_MISO Slave In/Master Out. - - - - - - - - CSPI2_SS0 Slave Select (Selectable polarity). Slave Select (Selectable polarity). Slave Select (Selectable polarity). Serial Clock. - - - - - - - - CSPI2_SS1 - - sw_mux_ctl_ CSPI3_ CSPI1_ cspi2_ss1 SS1 SS3 [6:0] sw_mux_ctl_ I2C3_S cspi2_ss2 DA [6:0] sw_mux_ctl_ I2C3_S cspi2_sclk CL [6:0] sw_mux_ctl_ cspi2_spi_ rdy[6:0] - IPU_FL ASH_S TROBE - - - - - - CSPI2_SS2 - - - - - - - CSPI2_SCLK - - - - - - - CSPI2_SPI_ RDY RXD1 - - - - - - - - - Rx Data. (+CE Bus 12) TRSTB - sw_mux_ctl_ USBOT PP4_TX rxd1[6:0] G_DATA DAT/ 4 STDA sw_mux_ctl_ USBOT PP4_TX txd1[6:0] G_DATA CLK/ 1 SCK sw_mux_ctl_ rts1[6:0] sw_mux_ctl_ cts1[6:0] - - PP4_TX FS/FS - - DSR_ DCE1 RI_DCE 1 DCD_D CE1 - - - MCU2_ 4 MCU2_ 5 MCU2_ 6 MCU2_ 7 TXD1 Tx Data. + (CE Bus 10) TCK - - - - RTS1 CTS1 Request to send. + (CE Bus 9) - DE - - - - - - - - UART1_ Clear to send. + CE Bus 8) GPS i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 31 Signal Descriptions Table 4. Functional Multiplexing (continued) Pin Name Group DTR_DCE1 UART1_ GPS Full UART IF Full UART IF Full UART IF Full UART IF Full UART IF Full UART IF Full UART IF Full UART IF UART2_ IR UART2_ IR UART2_ IR UART2_ IR 1-Wire Keypad Description CE Bus 11 HW Hardware Mode Mode 1 2 TMS - SW_ MUX_ EN sw_mux_ctl_ dtr_dce1[6:0] Alt Alt Alt Alt Alt Alt Mode Mode Mode Mode Mode Mode GPIO 1 2 3 4 5 6 - PP4_RX DAT/SR DA TXD1 - - - - MCU2_ 8 MCU2_ 9 MCU2_ 10 MCU2_ 11 MCU2_ 12 MCU2_ 13 MCU2_ 14 MCU2_ 15 MCU2_ 16 MCU1_ 27 MCU1_ 28 - - MCU2_ 17 - DSR_DCE1 Full UART IF + CE Bus 4 TDO USBOT sw_mux_ctl_ CSPI1_ G_DATA dsr_dce1[6:0 SCLK 3 ] USBOT sw_mux_ctl_ CSPI1_ G_DATA ri_dce1[6:0] SPI_RD 4 Y USBOT sw_mux_ctl_ CSPI1_ G_DATA dcd_dce1 SS3 5 [6:0] - - - - sw_mux_ctl_ dtr_dte1[6:0] - DSR_D CE2 RI_DCE 2 DCD_D CE2 DTR_D TE2 - - - - RI_DCE1 Full UART IF + CE Bus 5 TDI RXD1 - - - DCD_DCE1 Full UART IF + CE Bus 6 RESET_IN RTS1 USB_P WR - - - - - - DTR_DTE1 DSR_DTE1 RI_DTE1 DCD_DTE1 - - - - CSPI1_MOSI CSPI1_MISO CSPI1_SS0 CSPI1_SS1 - - EVNTB US_16 EVNTB US_17 EVNTB US_18 EVNTB US_19 - - - - - - - - - - - sw_mux_ctl_ DSR_D dsr_dte1[6:0] TE2 sw_mux_ctl_ RI_DTE I2C2_S IPU_DI ri_dte1[6:0] 2 CL AGB[25] sw_mux_ctl_ dcd_dte1 [6:0] sw_mux_ctl_ dtr_dce2[6:0] sw_mux_ctl_ rxd2[6:0] sw_mux_ctl_ txd2[6:0] sw_mux_ctl_ rts2[6:0] sw_mux_ctl_ cts2[6:0] sw_mux_ctl_ batt_line[6:0] sw_mux_ctl_ key_row0 [6:0] sw_mux_ctl_ key_row1 [6:0] sw_mux_ctl_ key_row2 [6:0] sw_mux_ctl_ key_row3 [6:0] sw_mux_ctl_ key_row4 [6:0] sw_mux_ctl_ key_row5 [6:0] sw_mux_ctl_ key_row6 [6:0] sw_mux_ctl_ key_row7 [6:0] sw_mux_ctl_ key_col0 [6:0] DCD_ DTE2 - - - - - - - I2C2_S IPU_DI DA AGB[26] - - - - - - - IPU_DI AGB[27] IPU_DI AGB[28] IPU_DI AGB[29] IPU_DI AGB[30] IPU_DI AGB[31] - - DTR_DCE2 RXD2 TXD2 RTS2 CTS2 BATT_LINE KEY_ROW0 - Tx Data. Tx Data. Request to send. Clear to send. One Wire Data keypad row sense 0 CSPI1_SS2 ipp_ind_firi_ rxd ipp_do_firi_ txd ipp_ind_firi_ rxd ipp_do_firi_ txd - - - - - - - - - - - - - - - - - - - - - - - KEY_ROW1 Keypad keypad row sense 1 - - - - - - - - - KEY_ROW2 Keypad keypad row sense 2 - - - - - - - - - KEY_ROW3 Keypad keypad row sense 3 - - - - - TRACE CTL TRACE CLK TRACE DATA_0 TRACE DATA_1 TRACE DATA_2 - - - - KEY_ROW4 Keypad keypad row sense 4 - - - - - - - MCU2_ 18 MCU2_ 19 MCU2_ 20 MCU2_ 21 - KEY_ROW5 Keypad keypad row sense 5 - - - - - - - KEY_ROW6 Keypad keypad row sense 6 ATA_INTRQ - - - - - - KEY_ROW7 Keypad keypad row sense 7 ATA_ BUFFER_EN - - - - - - - KEY_COL0 Keypad keypad column driver 0 - - - - - - i.MX31/i.MX31L Advance Information, Rev. 1.4 32 Preliminary Freescale Semiconductor Signal Descriptions Table 4. Functional Multiplexing (continued) Pin Name Group KEY_COL1 Keypad Description keypad column driver 1 HW Hardware Mode Mode 1 2 - - SW_ MUX_ EN sw_mux_ctl_ key_col1 [6:0] sw_mux_ctl_ key_col2 [6:0] sw_mux_ctl_ key_col3 [6:0] sw_mux_ctl_ key_col4 [6:0] sw_mux_ctl_ key_col5 [6:0] sw_mux_ctl_ key_col6 [6:0] sw_mux_ctl_ key_col7 [6:0] - sw_mux_ctl_ tck[6:0] sw_mux_ctl_ tms[6:0] sw_mux_ctl_ tdi[6:0] - sw_mux_ctl_ trstb[6:0] sw_mux_ctl_ de_b[6:0] - sw_mux_ctl_ usb_pwr[6:0] sw_mux_ctl_ usb_oc[6:0] sw_mux_ctl_ usb_byp[6:0] sw_mux_ctl_ usbotg_clk [6:0] sw_mux_ctl_ usbotg_dir [6:0] sw_mux_ctl_ usbotg_stp [6:0] sw_mux_ctl_ usbotg_nxt [6:0] sw_mux_ctl_ usbotg_ data0[6:0] Alt Alt Alt Alt Alt Alt Mode Mode Mode Mode Mode Mode GPIO 1 2 3 4 5 6 - - - - - - - KEY_COL2 Keypad keypad column driver 2 - - - - - - - - - KEY_COL3 Keypad keypad column driver 3 - - - - - TRACE DATA_3 TRACE DATA_4 TRACE DATA_5 TRACE DATA_6 TRACE DATA_7 - - - - - - - - - - - - KEY_COL4 Keypad keypad column driver 4 ATA_DMARQ - - - - - - MCU2_ 22 MCU2_ 23 MCU2_ 24 MCU2_ 25 - - - - - - - - KEY_COL5 Keypad keypad column driver 5 ATA_DA0 - - - - - - KEY_COL6 Keypad keypad column driver 6 ATA_DA1 - - - - - - KEY_COL7 Keypad keypad column driver 7 ATA_DA2 - - - - - - RTCK TCK TMS TDI TDO TRSTB DE SJC_MOD USB_PWR JTAG JTAG JTAG JTAG JTAG JTAG JTAG JTAG USB GEN USB GEN USB GEN USBOTG ARM Debug Test Clock JTAG TAP clock No MUX allowed JTAG TAP mode select No MUX allowed JTAG Tap Data In No MUX allowed JTAG TAP data out JTAG TAP reset No MUX allowed JTAG Debug Enable No MUX allowed JTAG Mode USB Generic - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - MAX1_ MCU1_ HMAST 29 ER_0 MAX1_ MCU1_ HMAST 30 ER_1 MAX1_ MCU1_ HMAST 31 ER_2 MAX1_ HMAST ER_3 MAX0_ HMAST ER_0 MAX0_ HMAST ER_1 MAX0_ HMAST ER_2 MAX0_ HMAST ER_3 - USB_OC USB Generic - - - - - - - USB_BYP USB Generic - - - - - - - USBOTG_ CLK USB OTG FS/ULPI Port - - - - - - - USBOTG_DIR USBOTG USB OTG FS/ULPI Port - - - - - - - - USBOTG_ STP USBOTG_ NXT USBOTG_ DATA0 USBOTG USB OTG FS/ULPI Port - - - - - - - - USBOTG USB OTG FS/ULPI Port - - - - - - - - USBOTG USB OTG FS/ULPI Port + CE Bus - - - UART4_ CTS - - - - i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 33 Signal Descriptions Table 4. Functional Multiplexing (continued) Pin Name Group USBOTG_ DATA1 USBOTG_ DATA2 USBOTG_ DATA3 USBOTG_ DATA4 USBOTG_ DATA5 USBOTG_ DATA6 USBOTG_ DATA7 USBH2_CLK USBOTG Description USB OTG FS/ULPI Port HW Hardware Mode Mode 1 2 - - SW_ MUX_ EN sw_mux_ctl_ usbotg_data 1[6:0] sw_mux_ctl_ usbotg_data 2[6:0] sw_mux_ctl_ usbotg_data 3[6:0] sw_mux_ctl_ usbotg_data 4[6:0] sw_mux_ctl_ usbotg_data 5[6:0] sw_mux_ctl_ usbotg_data 6[6:0] sw_mux_ctl_ usbotg_data 7[6:0] Alt Alt Alt Alt Alt Alt Mode Mode Mode Mode Mode Mode GPIO 1 2 3 4 5 6 - - - - - - - USBOTG USB OTG FS/ULPI Port + CE Bus USBOTG USB OTG FS/ULPI Port - - - - - - - - - - - - UART4_ RXD UART4_ TXD UART4_ RTS - - - - - - USBOTG USB OTG FS/ULPI Port - - - - - - - - USBOTG USB OTG FS/ULPI Port - - - - - - - - USBOTG USB OTG FS/ULPI Port - - - - - - - - USBOTG USB OTG FS/ULPI Port - - - - - - - - - USBH2 USB Host2 FS/ULPI ATA_INTRQ - sw_mux_ctl_ UART5_ usbh2_ RTS clk[6:0] sw_mux_ctl_ UART5_ usbh2_ RXD dir[6:0] sw_mux_ctl_ UART5_ usbh2_ TXD stp[6:0] sw_mux_ctl_ UART5_ usbh2_ CTS nxt[6:0] sw_mux_ctl_ usbh2_data0 [6:0] sw_mux_ctl_ usbh2_data1 [6:0] sw_mux_ctl_ ld0[6:0] sw_mux_ctl_ ld1[6:0] sw_mux_ctl_ ld2[6:0] sw_mux_ctl_ ld3[6:0] sw_mux_ctl_ ld4[6:0] sw_mux_ctl_ ld5[6:0] sw_mux_ctl_ ld6[6:0] - - - TRACE DATA_2 0 TRACE DATA_2 1 TRACE DATA_2 2 TRACE DATA_2 3 TRACE CTL TRACE CLK - - - - USBH2_DIR USBH2 USB Host2 FS/ULPI ATA_BUFFE R_EN ATA_DMARQ - - - - - - USBH2_STP USBH2 USB Host2 FS/ULPI - - - - - - USBH2_NXT USBH2 USB Host2 FS/ULPI ATA_DA0 - - - - - - USBH2_ DATA0 USBH2_ DATA1 LD0 USBH2 USB Host2 FS/ULPI ATA_DA1 - - - - - - USBH2 USB Host2 FS/ULPI ATA_DA2 - - - - - - - IPU (LCD) IPU (LCD) IPU (LCD) IPU (LCD) IPU (LCD) IPU (LCD) IPU (LCD) - - - - - - - SDMA_ DEBUG _PC_0 SDMA_ DEBUG _PC_1 SDMA_ DEBUG _PC_2 SDMA_ DEBUG _PC_3 SDMA_ DEBUG _PC_4 SDMA_ DEBUG _PC_5 SDMA_ DEBUG _PC_6 - LD1 - - - - - - - - - LD2 - - - - - - - - - LD3 - - - - - - - - - LD4 - - - - - - - - - LD5 - - - - - - - - - LD6 - - - - - - - - - i.MX31/i.MX31L Advance Information, Rev. 1.4 34 Preliminary Freescale Semiconductor Signal Descriptions Table 4. Functional Multiplexing (continued) Pin Name Group LD7 IPU (LCD) IPU (LCD) IPU (LCD) IPU (LCD) IPU (LCD) IPU (LCD) IPU (LCD) IPU (LCD) Description - HW Hardware Mode Mode 1 2 - - SW_ MUX_ EN sw_mux_ctl_ ld7[6:0] sw_mux_ctl_ ld8[6:0] sw_mux_ctl_ ld9[6:0] sw_mux_ctl_ ld10[6:0] sw_mux_ctl_ ld11[6:0] sw_mux_ctl_ ld12[6:0] sw_mux_ctl_ ld13[6:0] sw_mux_ctl_ ld14[6:0] Alt Alt Alt Alt Alt Alt Mode Mode Mode Mode Mode Mode GPIO 1 2 3 4 5 6 - - - - - SDMA_ DEBUG _PC_7 SDMA_ DEBUG _PC_8 SDMA_ DEBUG _PC_9 SDMA_ DEBUG _PC_10 SDMA_ DEBUG _PC_11 SDMA_ DEBUG _PC_12 SDMA_ DEBUG _PC_13 SDMA_ DEBUG _EVEN T_CHA NNEL_0 SDMA_ DEBUG _EVEN T_CHA NNEL_1 SDMA_ DEBUG _EVEN T_CHA NNEL_2 SDMA_ DEBUG _EVEN T_CHA NNEL_3 SDMA_ DEBUG _EVEN T_CHA NNEL_4 SDMA_ DEBUG _EVEN T_CHA NNEL_5 SDMA_ DEBUG _CORE _STATU S_0 SDMA_ DEBUG _CORE _STATU S_1 - LD8 - - - - - - - - - LD9 - - - - - - - - - LD10 - - - - - - - - - LD11 - - - - - - - - - LD12 - - - - - - - - - LD13 - - - - - - - - - LD14 - - - - - - - - - LD15 IPU (LCD) - - - sw_mux_ctl_ ld15[6:0] - - - - - - LD16 IPU (LCD) - - - sw_mux_ctl_ ld16[6:0] - - - - - - LD17 IPU (LCD) - - - sw_mux_ctl_ ld17[6:0] - - - - - - VSYNC0 IPU (LCD) frame sync - - sw_mux_ctl_ vsync0[6:0] - - - - - - HSYNC IPU (LCD) line sync - - sw_mux_ctl_ hsync[6:0] - - - - - - FPSHIFT IPU (LCD) shift - - sw_mux_ctl_ DISPB_ fpshift[6:0] BCLK - - - - - DRDY0 IPU (LCD) DRDY/VLD - - sw_mux_ctl_ drdy0[6:0] - - - - - - i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 35 Signal Descriptions Table 4. Functional Multiplexing (continued) Pin Name Group SD_D_I IPU (LCD) Description Data in for Serial Display HW Hardware Mode Mode 1 2 - - SW_ MUX_ EN sw_mux_ctl_ sd_d_i[6:0] Alt Alt Alt Alt Alt Alt Mode Mode Mode Mode Mode Mode GPIO 1 2 3 4 5 6 - SD_D_I - - - SDMA_ MCU3_ DEBUG 20 _CORE _STATU S_2 SDMA_ MCU3_ DEBUG 21 _CORE _STATU S_3 - MCU3_ 22 MCU3_ 23 MCU3_ 24 MCU3_ 25 - - - - - - - - MCU2_ 26 MCU2_ 27 MCU2_ 28 MCU2_ 29 MCU2_ 30 MCU2_ 31 MCU3_ 26 MCU3_ 27 MCU3_ 28 SD_D_IO IPU (LCD) Data in/out for Serial Display - - sw_mux_ctl_ sd_d_io[6:0] - - - - - SD_D_CLK IPU (LCD) IPU (LCD) IPU (LCD) IPU (LCD) IPU (LCD) IPU (LCD) IPU (LCD) IPU (LCD) IPU (LCD) IPU (LCD) IPU (LCD) IPU (LCD) SD/MMC 1 SD/MMC 1 SD/MMC 1 SD/MMC 1 SD/MMC 1 SD/MMC 1 ATA ATA ATA Serial Display clock - - sw_mux_ctl_ sd_d_clk[6:0 ] - - - - - LCS0 LCS1 SER_RS PAR_RS WRITE READ VSYNC3 CONTRAST D3_REV D3_CLS D3_SPL SD1_CMD Asynch. Port chip select Asynch. Port chip select Asynch. Serial Port data/comm Asynch.Parallel Port data/comm Asynch. Port write Asynch. Port read vsync - - - - - - - - - - - - - - - - - - - - - - - - - - - - - sw_mux_ctl_ DISPB_ lcs0[6:0] BCLK sw_mux_ctl_ lcs1[6:0] sw_mux_ctl_ ser_rs[6:0] sw_mux_ctl_ par_rs[6:0] sw_mux_ctl_ write[6:0] sw_mux_ctl_ read[6:0] sw_mux_ctl_ vsync3[6:0] sw_mux_ctl_ contrast[6:0] sw_mux_ctl_ d3_rev[6:0] sw_mux_ctl_ d3_cls[6:0] sw_mux_ctl_ d3_spl[6:0] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - TRACE DATA_0 TRACE DATA_1 TRACE DATA_2 TRACE DATA_3 TRACE DATA_4 - - - - - - - - - - - - - - - - - - - - - - - - sw_mux_ctl_ MSHC1 _SCLK sd1_ cmd[6:0] sw_mux_ctl_ MSHC1 sd1_clk[6:0] _BS sw_mux_ctl_ MSHC1 sd1_ _SDIO_ data0[6:0] DATA0 sw_mux_ctl_ MSHC1 sd1_ _DATA1 data1[6:0] sw_mux_ctl_ MSHC1 sd1_ _DATA2 data2[6:0] SD1_CLK SD1_DATA0 - - - - - - - - - - - - - - SD1_DATA1 - - - - - - - SD1_DATA2 - - - - - - - SD1_DATA3 - - - sw_mux_ctl_ MSHC1 CTI_TRI sd1_ _DATA3 G_IN_1 data3[6:0] _7 sw_mux_ctl_ UART4_ CSI_D0 ata_cs0[6:0] RXD sw_mux_ctl_ UART4_ CSI_D1 ata_cs1[6:0] RTS sw_mux_ctl_ UART4_ CSI_D2 ata_dior[6:0] TXD - TRACE obs_int_ DATA_5 5 TRACE DATA_6 - - ATA_CS0 ATA_CS1 ATA_DIOR - - - - - - - - - SD_D_ CLK LCS1 SER_R S - - - TRACE obs_int_ DATA_7 6 TRACE obs_int_ CTL 7 i.MX31/i.MX31L Advance Information, Rev. 1.4 36 Preliminary Freescale Semiconductor Signal Descriptions Table 4. Functional Multiplexing (continued) Pin Name Group ATA_DIOW ATA Description - HW Hardware Mode Mode 1 2 - - SW_ MUX_ EN Alt Alt Alt Alt Alt Alt Mode Mode Mode Mode Mode Mode GPIO 1 2 3 4 5 6 - TRACE obs_int_ CLK 8 - obs_int_ 9 - - MCU3_ 29 MCU3_ 30 MCU3_ 31 - - sw_mux_ctl_ UART4_ CSI_D3 ata_ CTS diow[6:0] sw_mux_ctl_ SD_D_ ata_ O dmack[6:0] sw_mux_ctl_ ata_ reset_b[6:0] - - SD_D - ATA_DMACK ATA - - - - - ATA_RESET ATA - - - - - - - CE_ CONTROL CLKSS CE CONTROL - Clock Source Select at reset Master Out/Slave In. - - - - - - - - - - - - - - - - Clock & Reset& PM CSPI3_ MM CSPI3_ MM CSPI3_ MM CSPI3_ MM TTM_ PAD QVDD PLL's PLL's PLL's PLL's PLL's PLL's PLL's PLL's Noisy Noisy Noisy Noisy Noisy Noisy Noisy Noisy Noisy Noisy Noisy Noisy Noisy Noisy Noisy Noisy Noisy CSPI3_MOSI - - sw_mux_ctl_ cspi3_ mosi[6:0] sw_mux_ctl_ cspi3_ miso[6:0] sw_mux_ctl_ cspi3_ sclk[6:0] sw_mux_ctl_ cspi3_spi_ rdy[6:0] - - - - - - - - - - - - - - - - - - - - - - - - - - - RXD3 - - - - - - CSPI3_MISO Slave In/Master Out. - - TXD3 - - - - - - CSPI3_SCLK Serial Clock. - - RTS3 - - - - - - CSPI3_SPI_ RDY TTM_PAD IOQVDD MVCC MGND UVCC UGND FVCC FGND SVCC SGND NVCC1 NVCC2 NVCC3 NVCC4 NVCC5 NVCC6 NVCC7 NVCC8 NVCC9 NVCC10 NVCC10 NVCC21 NVCC22 NGND1 NGND2 NGND3 NGND4 Serial Data Ready. - - CTS3 - - - - - - Special TTM pad1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 37 Signal Descriptions Table 4. Functional Multiplexing (continued) Pin Name Group NGND5 NGND6 NGND7 NGND8 NGND9 NGND10 NGND21 NGND22 QVCC QVCC1 4 1 Description - - - - - - - - - - - HW Hardware Mode Mode 1 2 - - - - - - - - - - - - - - - - - - - - - - SW_ MUX_ EN - - - - - - - - - - - Alt Alt Alt Alt Alt Alt Mode Mode Mode Mode Mode Mode GPIO 1 2 3 4 5 6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Noisy Noisy Noisy Noisy Noisy Noisy Noisy Noisy Quiet Quiet Quiet The special TTM pad (at U20) is used by Freescale internally and must be connected to GND on the customer's production board. 3.1.2 Pad Settings Table 5 shows the legend for the pin settings. Table 6 defines all the settings of each pad. If a pad's settings is configurable by software, then the bit controlling this setting is described in that table. Table 5. Pad Settings Legend Term Slew Rate Loopback Defines the speed of the pad (fast or slow). Enables the input buffer when the output buffer is enabled. Description Drive Strength Control Defines the driving strength of the pad. Pull Value Pull/Keep Select Pull/Keep Enable Open Drain Schmitt Trigger Supply Group Resistor value on the pad. The capability selected--pull or keeper. The signal has no meaning if pull/keeper enable is not enabled. Pull or keeper enabled or not. The signal that enables the open drain capability of the pad. The signal that enables the Schmidt trigger capability of the pad. The supply that the pad is connected to. i.MX31/i.MX31L Advance Information, Rev. 1.4 38 Preliminary Freescale Semiconductor Freescale Semiconductor i.MX31/i.MX31L Advance Information, Rev. 1.4 39 Preliminary Table 6. Pad Settings Pin Name Pad Slew Rate Loopback Drive Strength Enable (Max) Drive Strength Enable0 (High/ Normal) Pull Value Pull/ Keep Select Pull/ Keep Enable Open Drain Supply Schmitt Trigger Group Value After Reset value CAPTURE reset value GND reset GND value GND reset GND value GND reset value reset GND pu100 pu100 value pull reset value reset value GND reset GND value GND reset GND NVCC1 I regular sw_pad_ct slow l_capture[ 0] regular sw_pad_ct slow l_compare [0] slow slow pull sw_pad_ct VCC l_capture[ 8] pull VCC VCC COMPARE GND GND GND GND GND GND pu100 pu100 pull GND GND GND GND NVCC1 I WATCHDOG_ regular RST PWMO GPIO1_0 GND GND GND GND GND GND GND GND GND GND GND GND pu100 pu100 GND pu100 pu100 pull pull pull VCC VCC GND GND GND GND GND NVCC1 NVCC3 I I I regular sw_pad_ct slow l_pwmo[0] regular sw_pad_ct slow l_gpio1_0 [0] regular sw_pad_ct slow l_gpio1_1 [0] regular sw_pad_ct slow l_gpio1_2 [0] regular sw_pad_ct slow l_gpio1_3 [0] regular sw_pad_ct slow l_gpio1_4 [0] regular sw_pad_ct slow l_gpio1_5 [0] regular sw_pad_ct slow l_gpio1_6 [0] regular sw_pad_ct slow l_gpio3_0 [0] regular sw_pad_ct slow l_gpio3_1 [0] pull sw_pad_ct GND l_pwmo[8] GND sw_pad_ct VCC l_pwmo[4] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 sw_pad_ct pull sw_pad_ct VCC sw_pad_ct GND sw_pad_ct GND NVCC1 l_gpio1_0 l_gpio1_0 l_gpio1_0 l_gpio1_0 l_gpio1_0 l_gpio1_0 [2] [1] [7] [8] [3] [4] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 sw_pad_ct pull sw_pad_ct VCC sw_pad_ct GND sw_pad_ct GND NVCC1 l_gpio1_1 l_gpio1_1 l_gpio1_1 l_gpio1_1 l_gpio1_1 l_gpio1_1 [2] [1] [7] [8] [3] [4] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 sw_pad_ct pull sw_pad_ct VCC sw_pad_ct GND sw_pad_ct GND NVCC1 l_gpio1_2 l_gpio1_2 l_gpio1_2 l_gpio1_2 l_gpio1_2 l_gpio1_2 [2] [1] [7] [8] [3] [4] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 sw_pad_ct pull sw_pad_ct VCC sw_pad_ct GND sw_pad_ct GND NVCC1 l_gpio1_3 l_gpio1_3 l_gpio1_3 l_gpio1_3 l_gpio1_3 l_gpio1_3 [8] [3] [4] [2] [1] [7] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 sw_pad_ct pull sw_pad_ct VCC sw_pad_ct GND sw_pad_ct GND NVCC1 l_gpio1_4 l_gpio1_4 l_gpio1_4 l_gpio1_4 l_gpio1_4 l_gpio1_4 [2] [1] [7] [8] [3] [4] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 sw_pad_ct pull sw_pad_ct VCC sw_pad_ct GND sw_pad_ct GND NVCC1 l_gpio1_5 l_gpio1_5 l_gpio1_5 l_gpio1_5 l_gpio1_5 l_gpio1_5 [2] [1] [7] [8] [3] [4] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 sw_pad_ct pull sw_pad_ct VCC sw_pad_ct GND sw_pad_ct GND NVCC1 l_gpio1_6 l_gpio1_6 l_gpio1_6 l_gpio1_6 l_gpio1_6 l_gpio1_6 [2] [1] [7] [8] [3] [4] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 sw_pad_ct pull sw_pad_ct VCC sw_pad_ct GND sw_pad_ct GND NVCC4 l_gpio3_0 l_gpio3_0 l_gpio3_0 l_gpio3_0 l_gpio3_0 l_gpio3_0 [2] [1] [7] [8] [3] [4] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 sw_pad_ct pull sw_pad_ct VCC sw_pad_ct GND sw_pad_ct GND NVCC4 l_gpio3_1 l_gpio3_1 l_gpio3_1 l_gpio3_1 l_gpio3_1 l_gpio3_1 [2] [1] [7] [8] [3] [4] pull pull pull pull pull pull sw_pad_ct VCC l_sclk0[8] pull sw_pad_ct VCC l_srst0[8] pull sw_pad_ct VCC l_sven0[8] pull sw_pad_ct VCC l_stx0[8] pull sw_pad_ct VCC l_srx0[8] GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND NVCC9 GND NVCC9 GND NVCC9 GND NVCC9 GND NVCC9 GPIO1_1 GND I GPIO1_2 GND I GPIO1_3 GND I GPIO1_4 GND I GPIO1_5 GND I GPIO1_6 GND I GPIO3_0 GND I GPIO3_1 GND I SCLK0 SRST0 SVEN0 STX0 SRX0 regular sw_pad_ct slow sw_pad_ct GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_sclk0[0] l_sclk0[9] l_sclk0[2] l_sclk0[1] regular sw_pad_ct slow l_srst0[0] regular sw_pad_ct slow l_sven0[0] GND GND GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_srst0[2] l_srst0[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_sven0[2] l_sven0[1] I I Signal Descriptions I I I regular sw_pad_ct slow sw_pad_ct VCC sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_stx0[0] l_stx0[9] l_stx0[2] l_stx0[1] regular sw_pad_ct slow l_srx0[0] GND GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_srx0[2] l_srx0[1] Table 6. Pad Settings (continued) Pin Name Pad Slew Rate Loopback Drive Strength Enable (Max) Drive Strength Enable0 (High/ Normal) Pull Value Pull/ Keep Select Pull/ Keep Enable Open Drain Supply Schmitt Trigger Group Value After Reset 40 SIMPD0 regular sw_pad_ct slow l_simpd0 [0] regular regular regular ddr slow slow slow fast slow slow slow slow slow slow slow slow slow slow slow slow fast fast fast fast fast fast fast fast fast fast fast fast fast slow slow slow fast slow slow slow slow slow slow slow slow slow slow slow slow fast fast fast fast fast fast fast fast fast fast fast fast fast GND CKIH RESET_IN POR CLKO GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC GND GND GND GND GND GND GND GND GND GND GND GND BOOT_MODE0 regular BOOT_MODE1 regular BOOT_MODE2 regular Signal Descriptions GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_simpd0 l_simpd0 [2] [1] GND GND GND VCC GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC GND pu100 pu100 GND pu100 pu100 GND pu100 pu100 VCC pu100 pu100 GND pu100 pu100 GND pu100 pu100 GND pu100 pu100 GND pu100 pu100 GND pu100 pu100 GND pu100 pu100 GND pd100 pd100 GND pu100 pu100 GND pu100 pu100 GND pu100 pu100 GND pu100 pu100 GND pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 pull pull sw_pad_ct VCC l_simpd0 [8] pull pull pull pull pull pull pull pull pull pull pull pull pull pull pull pull pull pull pull pull pull pull pull pull pull pull pull pull pull GND VCC VCC GND GND GND GND GND GND GND VCC GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC GND GND GND GND GND GND GND GND VCC GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND NVCC9 I pull pull pull pull pull pull pull pull pull pull pull pull pull pull pull pull pull pull pull pull pull pull pull pull pull pull pull pull pull GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND sw_pad_ct VCC l_ckih[4] GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC GND GND GND GND GND GND VCC GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC NVCC1 NVCC1 NVCC1 I I I H I I I I I I I L L L L L L L L L L L L L L L L L L GND NVCC1 GND NVCC1 GND NVCC1 GND NVCC1 GND NVCC1 GND NVCC1 VCC NVCC1 GND NVCC1 GND NVCC1 GND NVCC1 GND NVCC1 GND NVCC1 GND NVCC1 GND NVCC22 GND NVCC22 GND NVCC22 GND NVCC22 GND NVCC22 GND NVCC22 GND NVCC22 GND NVCC22 GND NVCC22 GND NVCC22 GND NVCC2 GND NVCC22 GND NVCC22 i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor BOOT_MODE3 regular BOOT_MODE4 regular CKIL VSTBY DVFS0 DVFS1 VPG0 VPG1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 MA10 A11 regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular POWER_FAIL regular Preliminary GND sw_pad_ct VCC l_a0[2] GND sw_pad_ct VCC l_a1[2] GND sw_pad_ct VCC l_a2[2] GND sw_pad_ct VCC l_a3[2] GND sw_pad_ct VCC l_a4[2] GND sw_pad_ct VCC l_a5[2] GND sw_pad_ct VCC l_a6[2] GND sw_pad_ct VCC l_a7[2] GND sw_pad_ct VCC l_a8[2] GND sw_pad_ct VCC l_a9[2] GND sw_pad_ct VCC l_a10[2] GND sw_pad_ct VCC l_ma10[2] GND sw_pad_ct VCC l_a11[2] Table 6. Pad Settings (continued) Pin Name Pad Slew Rate Loopback Drive Strength Enable (Max) Drive Strength Enable0 (High/ Normal) Pull Value Pull/ Keep Select Pull/ Keep Enable Open Drain Supply Schmitt Trigger Group Value After Reset Freescale Semiconductor i.MX31/i.MX31L Advance Information, Rev. 1.4 41 Preliminary A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 SDBA1 SDBA0 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular ddr ddr ddr ddr ddr ddr ddr ddr ddr fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND sw_pad_ct VCC l_a12[2] GND sw_pad_ct VCC l_a13[2] GND sw_pad_ct VCC l_a14[2] GND sw_pad_ct VCC l_a15[2] GND sw_pad_ct VCC l_a16[2] GND sw_pad_ct VCC l_a17[2] GND sw_pad_ct VCC l_a18[2] GND sw_pad_ct VCC l_a19[2] GND sw_pad_ct VCC l_a20[2] GND sw_pad_ct VCC l_a21[2] GND sw_pad_ct VCC l_a22[2] GND sw_pad_ct VCC l_a23[2] GND sw_pad_ct VCC l_a24[2] GND sw_pad_ct VCC l_a25[2] GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC GND GND VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 GND pu100 pu100 GND pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 pull pull pull pull pull pull pull pull pull pull pull pull pull pull pull pull keep keep keep keep keep keep keep keep keep pull pull pull pull pull pull pull pull pull pull pull pull pull pull pull pull keep keep keep keep keep keep keep keep keep GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCC VCC VCC GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCC VCC VCC GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND NVCC22 GND NVCC22 GND NVCC21 GND NVCC21 GND NVCC21 GND NVCC22 GND NVCC22 GND NVCC22 GND NVCC22 GND NVCC22 GND NVCC22 GND NVCC22 GND NVCC22 GND NVCC22 GND NVCC22 GND NVCC22 GND NVCC21 GND NVCC21 GND NVCC21 GND NVCC21 GND NVCC21 GND NVCC21 GND NVCC21 GND NVCC21 GND NVCC21 L L L L L L L L L L L L L L L L I I I I I GND sw_pad_ct VCC l_sd0[2] GND sw_pad_ct VCC l_sd1[2] GND sw_pad_ct VCC l_sd2[2] GND sw_pad_ct VCC l_sd3[2] GND sw_pad_ct VCC l_sd4[2] GND sw_pad_ct VCC l_sd5[2] GND sw_pad_ct VCC l_sd6[2] GND sw_pad_ct VCC l_sd7[2] GND sw_pad_ct VCC l_sd8[2] Signal Descriptions I I I I Table 6. Pad Settings (continued) Pin Name Pad Slew Rate Loopback Drive Strength Enable (Max) Drive Strength Enable0 (High/ Normal) Pull Value Pull/ Keep Select Pull/ Keep Enable Open Drain Supply Schmitt Trigger Group Value After Reset 42 SD9 SD10 SD11 SD12 SD13 SD14 ddr ddr ddr ddr ddr ddr ddr ddr ddr ddr ddr ddr ddr ddr ddr ddr ddr ddr ddr ddr ddr ddr ddr ddr fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Signal Descriptions GND sw_pad_ct VCC l_sd9[2] GND sw_pad_ct VCC l_sd10[2] GND sw_pad_ct VCC l_sd11[2] GND sw_pad_ct VCC l_sd12[2] GND sw_pad_ct VCC l_sd13[2] GND sw_pad_ct VCC l_sd14[2] GND sw_pad_ct VCC l_sd15[2] GND sw_pad_ct VCC l_sd16[2] GND sw_pad_ct VCC l_sd17[2] GND sw_pad_ct VCC l_sd18[2] GND sw_pad_ct VCC l_sd19[2] GND sw_pad_ct VCC l_sd20[2] GND sw_pad_ct VCC l_sd21[2] GND sw_pad_ct VCC l_sd22[2] GND sw_pad_ct VCC l_sd23[2] GND sw_pad_ct VCC l_sd24[2] GND sw_pad_ct VCC l_sd25[2] GND sw_pad_ct VCC l_sd26[2] GND sw_pad_ct VCC l_sd27[2] GND sw_pad_ct VCC l_sd28[2] GND sw_pad_ct VCC l_sd29[2] GND sw_pad_ct VCC l_sd30[2] GND sw_pad_ct VCC l_sd31[2] GND sw_pad_ct VCC l_dqm0[2] VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 keep keep keep keep keep keep keep keep keep keep keep keep keep keep keep keep keep keep keep keep keep keep keep keep keep keep keep keep keep keep keep keep keep keep keep keep keep keep keep keep keep keep keep keep keep keep keep keep VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND NVCC21 GND NVCC22 GND NVCC22 GND NVCC22 GND NVCC22 GND NVCC22 GND NVCC22 GND NVCC22 GND NVCC22 GND NVCC22 GND NVCC22 GND NVCC22 GND NVCC22 GND NVCC22 GND NVCC22 GND NVCC22 GND NVCC22 GND NVCC22 GND NVCC22 GND NVCC22 GND NVCC22 GND NVCC22 GND NVCC22 GND NVCC2 I I I I I I I I I I I I I I I I I I I I I I I I i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor SD15 SD16 SD17 SD18 SD19 SD20 SD21 SD22 SD23 SD24 SD25 SD26 SD27 SD28 SD29 SD30 SD31 DQM0 Preliminary Table 6. Pad Settings (continued) Pin Name Pad Slew Rate Loopback Drive Strength Enable (Max) Drive Strength Enable0 (High/ Normal) Pull Value Pull/ Keep Select Pull/ Keep Enable Open Drain Supply Schmitt Trigger Group Value After Reset Freescale Semiconductor i.MX31/i.MX31L Advance Information, Rev. 1.4 43 Preliminary DQM1 DQM2 DQM3 EB0 EB1 OE CS0 CS1 CS2 CS3 CS4 CS5 ECB LBA BCLK RW RAS CAS SDWE SDCKE0 SDCKE1 SDCLK SDCLK SDQS0 SDQS1 SDQS2 SDQS3 ddr ddr ddr regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular ddr ddr ddr ddr ddr ddr fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC GND GND GND GND GND GND VCC VCC GND GND GND GND GND sw_pad_ct VCC l_dqm1[2] GND sw_pad_ct VCC l_dqm2[2] GND sw_pad_ct VCC l_dqm3[2] GND sw_pad_ct GND l_eb0[2] GND sw_pad_ct GND l_eb1[2] GND sw_pad_ct GND l_oe[2] GND sw_pad_ct GND l_cs0[2] GND sw_pad_ct GND l_cs1[2] GND sw_pad_ct VCC l_cs2[2] GND sw_pad_ct VCC l_cs3[2] GND sw_pad_ct GND l_cs4[2] GND sw_pad_ct GND l_cs5[2] GND sw_pad_ct GND l_ecb[2] GND sw_pad_ct GND l_lba[2] VCC sw_pad_ct GND l_bclk[2] GND sw_pad_ct GND l_rw[2] GND sw_pad_ct VCC l_ras[2] GND sw_pad_ct VCC l_cas[2] GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC GND GND GND VCC VCC GND GND GND GND VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 GND pu100 pu100 GND pu100 pu100 GND pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 GND pd100 pd100 GND pd100 pd100 GND pd100 pd100 GND pd100 pd100 keep keep keep pull pull pull pull pull keep keep pull pull pull pull pull pull keep keep keep keep keep pull pull pull pull pull pull keep keep keep pull pull pull pull pull keep keep pull pull pull pull pull pull keep keep keep keep keep pull pull pull pull pull pull VCC VCC VCC GND GND GND GND GND VCC VCC GND GND VCC GND GND GND VCC VCC VCC VCC VCC GND GND VCC VCC VCC VCC VCC VCC VCC GND GND GND GND GND VCC VCC GND GND VCC GND GND GND VCC VCC VCC VCC VCC GND GND VCC VCC VCC VCC GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND NVCC2 GND NVCC2 GND NVCC21 GND NVCC2 GND NVCC2 GND NVCC2 GND NVCC2 GND NVCC2 GND NVCC2 GND NVCC2 GND NVCC2 GND NVCC2 GND NVCC2 GND NVCC2 GND NVCC2 GND NVCC2 GND NVCC2 GND NVCC2 GND NVCC2 GND NVCC2 GND NVCC2 GND NVCC2 GND NVCC2 GND NVCC21 GND NVCC22 GND NVCC22 GND NVCC22 I I I H H H H H H H H H H I I I I I I I I Signal Descriptions VCC sw_pad_ct VCC l_sdclk[2] VCC sw_pad_ct VCC l_sdclk[2] GND GND GND GND GND GND GND GND GND GND GND GND I I I I I I Table 6. Pad Settings (continued) Pin Name Pad Slew Rate Loopback Drive Strength Enable (Max) Drive Strength Enable0 (High/ Normal) Pull Value Pull/ Keep Select Pull/ Keep Enable Open Drain Supply Schmitt Trigger Group Value After Reset 44 NFWE regular sw_pad_ct fast l_nfwe_b [0] regular sw_pad_ct fast l_nfre_b[0] regular sw_pad_ct fast l_nfale[0] regular sw_pad_ct fast l_nfcle[0] regular sw_pad_ct fast l_nfwp_b [0] regular sw_pad_ct fast l_nfce_b [0] regular sw_pad_ct fast l_nfrb[0] regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast GND NFRE NFALE NFCLE NFWP GND GND GND GND Signal Descriptions GND sw_pad_ct GND sw_pad_ct VCC pd100 pd100 l_nfwe_b l_nfwe_b [2] [1] GND sw_pad_ct GND sw_pad_ct VCC pu100 pu100 l_nfre_b[2] l_nfre_b[1] GND sw_pad_ct GND sw_pad_ct VCC pu100 pu100 l_nfale[2] l_nfale[1] GND sw_pad_ct GND sw_pad_ct VCC pu100 pu100 l_nfcle[2] l_nfcle[1] GND sw_pad_ct GND sw_pad_ct VCC pu100 pu100 l_nfwp_b l_nfwp_b [2] [1] GND sw_pad_ct GND sw_pad_ct VCC pu100 pu100 l_nfce_b l_nfce_b [2] [1] GND sw_pad_ct GND sw_pad_ct VCC pu100 pu100 l_nfrb[2] l_nfrb[1] GND sw_pad_ct VCC l_d15[2] GND sw_pad_ct VCC l_d14[2] GND sw_pad_ct VCC l_d13[2] GND sw_pad_ct VCC l_d12[2] GND sw_pad_ct VCC l_d11[2] GND sw_pad_ct VCC l_d10[2] GND sw_pad_ct VCC l_d9[2] GND sw_pad_ct VCC l_d8[2] GND sw_pad_ct VCC l_d7[2] GND sw_pad_ct VCC l_d6[2] GND sw_pad_ct VCC l_d5[2] GND sw_pad_ct VCC l_d4[2] GND sw_pad_ct VCC l_d3[2] GND sw_pad_ct VCC l_d2[2] GND sw_pad_ct VCC l_d1[2] VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 pull pull sw_pad_ct VCC l_nfwe_b [8] pull sw_pad_ct VCC l_nfre_b[8] pull sw_pad_ct VCC l_nfale[8] pull sw_pad_ct VCC l_nfcle[8] pull sw_pad_ct VCC l_nfwp_b [8] pull sw_pad_ct VCC l_nfce_b [8] pull sw_pad_ct VCC l_nfrb[8] keep keep keep keep keep keep keep keep keep keep keep keep keep keep keep VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC GND GND GND GND NVCC10 I pull pull pull pull GND GND GND GND GND GND GND GND GND GND GND GND GND NVCC10 GND NVCC10 GND NVCC10 GND NVCC10 I I I I i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor NFCE GND pull GND GND GND GND NVCC10 I NFRB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND pull keep keep keep keep keep keep keep keep keep keep keep keep keep keep keep GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND NVCC10 GND NVCC10 GND NVCC10 GND NVCC10 GND NVCC10 GND NVCC10 GND NVCC10 GND NVCC10 GND NVCC10 GND NVCC10 GND NVCC10 GND NVCC10 GND NVCC10 GND NVCC10 GND NVCC10 GND NVCC10 I I I I I I I I I I I I I I I I Preliminary Table 6. Pad Settings (continued) Pin Name Pad Slew Rate Loopback Drive Strength Enable (Max) Drive Strength Enable0 (High/ Normal) Pull Value Pull/ Keep Select Pull/ Keep Enable Open Drain Supply Schmitt Trigger Group Value After Reset Freescale Semiconductor i.MX31/i.MX31L Advance Information, Rev. 1.4 45 Preliminary D0 PC_CD1 regular regular fast slow fast GND GND sw_pad_ct VCC l_d0[2] GND GND VCC VCC VCC pu100 pu100 VCC pu100 pu100 keep pull keep VCC VCC GND GND GND GND GND NVCC10 I I slow sw_pad_ct GND l_pc_cd1_ b[9] slow GND GND pull sw_pad_ct VCC l_pc_cd1_ b[8] pull sw_pad_ct VCC l_pc_cd2_ b[8] pull sw_pad_ct VCC l_pc_wait_ b[8] pull sw_pad_ct VCC l_pc_read y[8] pull sw_pad_ct VCC l_pc_pwro n[8] pull sw_pad_ct VCC l_pc_vs1[8 ] pull sw_pad_ct VCC l_pc_vs2[8 ] pull sw_pad_ct VCC l_pc_bvd1[ 8] pull sw_pad_ct VCC l_pc_bvd2[ 8] pull sw_pad_ct VCC l_pc_rst[8] pull sw_pad_ct VCC l_iois16[8] pull sw_pad_ct VCC l_pc_rw_b[ 8] pull pull pull GND GND VCC GND GND VCC GND sw_pad_ct GND NVCC3 l_pc_cd1_ b[4] GND GND GND NVCC3 PC_CD2 regular slow GND GND VCC VCC pu100 pu100 pull GND I PC_WAIT regular slow slow sw_pad_ct GND l_pc_wait_ b[9] slow sw_pad_ct GND l_pc_read y[9] slow sw_pad_ct GND l_pc_pwro n[9] slow sw_pad_ct GND l_pc_vs1[9 ] slow GND GND GND GND VCC VCC pu100 pu100 pull GND GND GND GND NVCC3 I PC_READY regular slow GND GND VCC VCC pu100 pu100 pull GND GND GND GND NVCC3 I PC_PWRON regular slow GND GND VCC VCC pd100 pd100 pull GND GND GND GND NVCC3 I PC_VS1 regular slow GND GND VCC VCC pu100 pu100 pull GND GND GND GND NVCC3 I PC_VS2 regular slow GND GND VCC VCC pu100 pu100 pull GND GND GND GND NVCC3 I PC_BVD1 regular slow slow GND GND GND GND VCC VCC pu100 pu100 pull GND GND GND GND NVCC3 I PC_BVD2 regular slow slow GND GND GND GND VCC VCC pu100 pu100 pull GND GND GND GND NVCC3 I PC_RST IOIS16 PC_RW regular regular regular slow slow slow slow slow slow GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 pull pull pull GND GND GND GND GND GND GND GND GND GND NVCC3 GND NVCC3 GND NVCC3 I I I PC_POE M_GRANT CSI_D4 CSI_D5 CSI_D6 CSI_D7 CSI_D8 regular regular slow slow slow slow slow slow GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC GND GND VCC pu100 pu100 GND pu100 pu100 GND pu100 pu100 pull pull pull GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND NVCC3 GND NVCC2 GND NVCC2 GND NVCC4 GND NVCC4 GND NVCC4 GND NVCC4 GND NVCC4 I I I I M_REQUEST regular regular sw_pad_ct fast l_csi_d4[0] regular sw_pad_ct fast l_csi_d5[0] regular sw_pad_ct fast l_csi_d6[0] regular sw_pad_ct fast l_csi_d7[0] regular sw_pad_ct fast l_csi_d8[0] GND sw_pad_ct GND sw_pad_ct VCC pu100 pu100 sw_pad_ct keep sw_pad_ct VCC l_csi_d4[2] l_csi_d4[1] l_csi_d4[7] l_csi_d4[8] GND sw_pad_ct GND sw_pad_ct VCC pu100 pu100 sw_pad_ct keep sw_pad_ct VCC l_csi_d5[2] l_csi_d5[1] l_csi_d5[7] l_csi_d5[8] GND sw_pad_ct GND sw_pad_ct VCC pu100 pu100 sw_pad_ct keep sw_pad_ct VCC l_csi_d6[2] l_csi_d6[1] l_csi_d6[7] l_csi_d6[8] GND sw_pad_ct GND sw_pad_ct VCC pu100 pu100 sw_pad_ct keep sw_pad_ct VCC l_csi_d7[2] l_csi_d7[1] l_csi_d7[7] l_csi_d7[8] GND sw_pad_ct GND sw_pad_ct VCC pu100 pu100 sw_pad_ct keep sw_pad_ct VCC l_csi_d8[2] l_csi_d8[1] l_csi_d8[7] l_csi_d8[8] Signal Descriptions I I I I Table 6. Pad Settings (continued) Pin Name Pad Slew Rate Loopback Drive Strength Enable (Max) Drive Strength Enable0 (High/ Normal) Pull Value Pull/ Keep Select Pull/ Keep Enable Open Drain Supply Schmitt Trigger Group Value After Reset 46 CSI_D9 CSI_D10 regular sw_pad_ct fast l_csi_d9[0] regular sw_pad_ct fast l_csi_d10 [0] regular sw_pad_ct fast l_csi_d11 [0] regular sw_pad_ct fast l_csi_d12 [0] regular sw_pad_ct fast l_csi_d13 [0] regular sw_pad_ct fast l_csi_d14 [0] regular sw_pad_ct fast l_csi_d15 [0] regular sw_pad_ct fast l_csi_mclk [0] GND GND CSI_D11 GND CSI_D12 GND CSI_D13 GND Signal Descriptions GND sw_pad_ct GND sw_pad_ct VCC pu100 pu100 sw_pad_ct keep sw_pad_ct VCC l_csi_d9[2] l_csi_d9[1] l_csi_d9[7] l_csi_d9[8] GND sw_pad_ct GND sw_pad_ct VCC pu100 pu100 sw_pad_ct keep sw_pad_ct VCC l_csi_d10 l_csi_d10 l_csi_d10[ l_csi_d10 [2] [1] 7] [8] GND sw_pad_ct GND sw_pad_ct VCC pu100 pu100 sw_pad_ct keep sw_pad_ct VCC l_csi_d11 l_csi_d11 l_csi_d11[ l_csi_d11 [2] [1] 7] [8] GND sw_pad_ct GND sw_pad_ct VCC pu100 pu100 sw_pad_ct keep sw_pad_ct VCC l_csi_d12 l_csi_d12 l_csi_d12[ l_csi_d12 [2] [1] 7] [8] GND sw_pad_ct GND sw_pad_ct VCC pu100 pu100 sw_pad_ct keep sw_pad_ct VCC l_csi_d13 l_csi_d13 l_csi_d13[ l_csi_d13 [2] [1] 7] [8] GND sw_pad_ct GND sw_pad_ct VCC pu100 pu100 sw_pad_ct keep sw_pad_ct VCC l_csi_d14 l_csi_d14[ l_csi_d14 l_csi_d14 [8] 7] [1] [2] GND sw_pad_ct GND sw_pad_ct VCC pu100 pu100 sw_pad_ct keep sw_pad_ct VCC l_csi_d15[ l_csi_d15 l_csi_d15 l_csi_d15 7] [8] [2] [1] GND sw_pad_ct GND sw_pad_ct VCC pu100 pu100 sw_pad_ct keep sw_pad_ct VCC l_csi_mclk l_csi_mclk l_csi_mclk l_csi_mclk [2] [1] [7] [8] GND sw_pad_ct GND sw_pad_ct VCC pu100 pu100 sw_pad_ct keep sw_pad_ct VCC l_csi_vsyn l_csi_vsyn l_csi_vsyn l_csi_vsyn c[2] c[1] c[7] c[8] GND sw_pad_ct GND sw_pad_ct VCC pu100 pu100 sw_pad_ct keep sw_pad_ct VCC l_csi_hsyn l_csi_hsyn l_csi_hsyn l_csi_hsyn c[2] c[1] c[7] c[8] GND sw_pad_ct GND sw_pad_ct VCC pu100 pu100 sw_pad_ct keep sw_pad_ct VCC l_csi_pixcl l_csi_pixcl l_csi_pixcl l_csi_pixcl k[2] k[1] k[7] k[8] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_i2c_clk l_i2c_clk [2] [1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_i2c_dat l_i2c_dat [2] [1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_stxd3[2] l_stxd3[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_srxd3[2] l_srxd3[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_sck3[2] l_sck3[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_sfs3[2] l_sfs3[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_stxd4[2] l_stxd4[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_srxd4[2] l_srxd4[1] pull GND GND GND GND GND GND GND NVCC4 GND NVCC4 I I GND GND GND GND NVCC4 I GND GND GND GND NVCC4 I GND GND GND GND NVCC4 I i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor CSI_D14 GND GND GND GND GND NVCC4 I CSI_D15 GND GND GND GND GND NVCC4 I CSI_MCLK GND GND GND GND GND NVCC4 I Preliminary CSI_VSYNC regular sw_pad_ct fast l_csi_vsyn c[0] CSI_HSYNC regular sw_pad_ct fast l_csi_hsyn c[0] CSI_PIXCLK regular sw_pad_ct fast l_csi_pixcl k[0] I2C_CLK regular sw_pad_ct slow l_i2c_clk [0] regular sw_pad_ct slow l_i2c_dat [0] regular sw_pad_ct slow l_stxd3[0] regular sw_pad_ct slow l_srxd3[0] regular sw_pad_ct slow l_sck3[0] regular sw_pad_ct slow l_sfs3[0] regular sw_pad_ct slow l_stxd4[0] regular sw_pad_ct slow l_srxd4[0] GND GND GND GND GND NVCC4 I GND GND GND GND GND NVCC4 I GND GND GND sw_pad_ct VCC l_csi_pixcl k[4] NVCC4 I GND pull sw_pad_ct VCC sw_pad_ct GND sw_pad_ct VCC l_i2c_clk l_i2c_clk l_i2c_clk [8] [3] [4] pull sw_pad_ct VCC sw_pad_ct GND l_i2c_dat l_i2c_dat [8] [3] pull sw_pad_ct VCC l_stxd3[8] pull sw_pad_ct VCC l_srxd3[8] pull sw_pad_ct VCC l_sck3[8] pull sw_pad_ct VCC l_sfs3[8] pull sw_pad_ct VCC l_stxd4[8] pull sw_pad_ct VCC l_srxd4[8] GND GND GND GND GND GND GND GND VCC VCC NVCC4 I I2C_DAT GND pull NVCC4 I STXD3 SRXD3 SCK3 SFS3 STXD4 SRXD4 GND GND GND GND GND GND pull pull pull pull pull pull GND GND GND NVCC10 GND NVCC10 I I I I I I GND sw_pad_ct VCC NVCC10 l_sck3[4] GND GND GND GND GND NVCC10 GND NVCC5 GND sw_pad_ct GND NVCC5 l_srxd4[4] Table 6. Pad Settings (continued) Pin Name Pad Slew Rate Loopback Drive Strength Enable (Max) Drive Strength Enable0 (High/ Normal) Pull Value Pull/ Keep Select Pull/ Keep Enable Open Drain Supply Schmitt Trigger Group Value After Reset Freescale Semiconductor i.MX31/i.MX31L Advance Information, Rev. 1.4 47 Preliminary SCK4 SFS4 STXD5 SRXD5 SCK5 SFS5 STXD6 SRXD6 SCK6 SFS6 regular sw_pad_ct slow l_sck4[0] regular sw_pad_ct slow l_sfs4[0] regular sw_pad_ct slow l_stxd5[0] regular sw_pad_ct slow l_srxd5[0] regular sw_pad_ct slow l_sck5[0] regular sw_pad_ct slow l_sfs5[0] regular sw_pad_ct slow l_stxd6[0] regular sw_pad_ct slow l_srxd6[0] regular sw_pad_ct slow l_sck6[0] regular sw_pad_ct slow l_sfs6[0] GND GND GND GND GND GND GND GND GND GND GND GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_sck4[2] l_sck4[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_sfs4[2] l_sfs4[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_stxd5[2] l_stxd5[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_srxd5[2] l_srxd5[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_sck5[2] l_sck5[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_sfs5[2] l_sfs5[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_stxd6[2] l_stxd6[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_srxd6[2] l_srxd6[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_sck6[2] l_sck6[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_sfs6[2] l_sfs6[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_cspi1_m l_cspi1_m osi[2] osi[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_cspi1_mi l_cspi1_mi so[2] so[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_cspi1_ss l_cspi1_ss 0[2] 0[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_cspi1_ss l_cspi1_ss 1[2] 1[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_cspi1_ss l_cspi1_ss 2[2] 2[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_cspi1_sc l_cspi1_sc lk[2] lk[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_cspi1_sp l_cspi1_sp i_rdy[2] i_rdy[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_cspi2_m l_cspi2_m osi[1] osi[2] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_cspi2_mi l_cspi2_mi so[2] so[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_cspi2_ss l_cspi2_ss 0[2] 0[1] pull pull pull pull pull pull pull pull pull pull pull pull sw_pad_ct VCC l_sck4[8] pull sw_pad_ct VCC l_sfs4[8] pull sw_pad_ct VCC l_stxd5[8] pull sw_pad_ct VCC l_srxd5[8] pull sw_pad_ct VCC l_sck5[8] pull sw_pad_ct VCC l_sfs5[8] pull sw_pad_ct VCC l_stxd6[8] pull sw_pad_ct VCC l_srxd6[8] pull sw_pad_ct VCC l_sck6[8] pull sw_pad_ct VCC l_sfs6[8] pull sw_pad_ct VCC l_cspi1_m osi[8] pull sw_pad_ct VCC l_cspi1_mi so[8] pull sw_pad_ct VCC l_cspi1_ss 0[8] pull sw_pad_ct VCC l_cspi1_ss 1[8] pull sw_pad_ct VCC l_cspi1_ss 2[8] pull sw_pad_ct VCC l_cspi1_sc lk[8] pull sw_pad_ct VCC l_cspi1_sp i_rdy[8] GND GND GND GND GND GND GND GND GND GND GND GND sw_pad_ct VCC l_sck4[4] NVCC5 I I I I I I I I I I I GND sw_pad_ct GND NVCC5 l_sfs4[4] GND GND GND GND GND NVCC5 GND NVCC5 NVCC5 GND sw_pad_ct VCC l_sck5[4] GND GND GND GND GND GND GND NVCC5 GND NVCC10 GND NVCC10 GND sw_pad_ct VCC NVCC10 l_sck6[4] GND GND GND GND GND NVCC10 GND NVCC10 CSPI1_MOSI regular sw_pad_ct slow l_cspi1_m osi[0] CSPI1_MISO regular sw_pad_ct slow l_cspi1_mi so[0] CSPI1_SS0 regular sw_pad_ct slow l_cspi1_ss 0[0] regular sw_pad_ct slow l_cspi1_ss 1[0] regular sw_pad_ct slow l_cspi1_ss 2[0] GND pull GND GND GND GND NVCC10 I GND pull GND GND GND GND NVCC10 I CSPI1_SS1 GND pull GND GND GND GND NVCC10 I CSPI1_SS2 GND pull GND GND GND GND NVCC10 I CSPI1_SCLK regular sw_pad_ct slow l_cspi1_sc lk[0] CSPI1_SPI_R regular sw_pad_ct slow DY l_cspi1_sp i_rdy[0] CSPI2_MOSI regular sw_pad_ct slow l_cspi2_m osi[0] CSPI2_MISO regular sw_pad_ct slow l_cspi2_mi so[0] CSPI2_SS0 regular sw_pad_ct slow l_cspi2_ss 0[0] GND pull GND GND sw_pad_ct VCC NVCC10 l_cspi1_sc lk[4] GND GND GND NVCC10 I GND pull GND I Signal Descriptions GND pull pull sw_pad_ct VCC sw_pad_ct GND l_cspi2_m l_cspi2_m osi[8] osi[3] pull sw_pad_ct VCC sw_pad_ct GND l_cspi2_mi l_cspi2_mi so[8] so[3] pull sw_pad_ct VCC l_cspi2_ss 0[8] GND GND VCC VCC NVCC5 I GND pull VCC VCC NVCC5 I GND pull GND GND NVCC5 I Table 6. Pad Settings (continued) Pin Name Pad Slew Rate Loopback Drive Strength Enable (Max) Drive Strength Enable0 (High/ Normal) Pull Value Pull/ Keep Select Pull/ Keep Enable Open Drain Supply Schmitt Trigger Group Value After Reset 48 CSPI2_SS1 regular sw_pad_ct slow l_cspi2_ss 1[0] regular sw_pad_ct slow l_cspi2_ss 2[0] GND CSPI2_SS2 GND CSPI2_SCLK regular sw_pad_ct slow l_cspi2_sc lk[0] CSPI2_SPI_R regular sw_pad_ct slow DY l_cspi2_sp i_rdy[0] RXD1 TXD1 RTS1 CTS1 DTR_DCE1 regular sw_pad_ct slow l_rxd1[0] regular sw_pad_ct slow l_txd1[0] regular sw_pad_ct slow l_rts1[0] regular sw_pad_ct slow l_cts1[0] regular sw_pad_ct slow l_dtr_dce1 [0] regular sw_pad_ct slow l_dsr_dce 1[0] regular sw_pad_ct slow l_ri_dce1 [0] regular sw_pad_ct slow l_dcd_dce 1[0] regular sw_pad_ct slow l_dtr_dte1[ 0] regular sw_pad_ct slow l_dsr_dte1 [0] regular sw_pad_ct slow l_ri_dte1 [0] regular sw_pad_ct slow l_dcd_dte 1[0] regular sw_pad_ct slow l_dtr_dce2 [0] regular sw_pad_ct slow l_rxd2[0] GND GND GND GND GND GND GND Signal Descriptions GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_cspi2_ss l_cspi2_ss 1[2] 1[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_cspi2_ss l_cspi2_ss 2[2] 2[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_cspi2_sc l_cspi2_sc lk[2] lk[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_cspi2_sp l_cspi2_sp i_rdy[2] i_rdy[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_rxd1[2] l_rxd1[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_txd1[2] l_txd1[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_rts1[2] l_rts1[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_cts1[2] l_cts1[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_dtr_dce1 l_dtr_dce1 [2] [1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_dsr_dce l_dsr_dce 1[2] 1[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_ri_dce1 l_ri_dce1 [2] [1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_dcd_dce l_dcd_dce 1[2] 1[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_dtr_dte1 l_dtr_dte1 [2] [1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_dsr_dte1 l_dsr_dte1 [2] [1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_ri_dte1 l_ri_dte1 [2] [1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_dcd_dte l_dcd_dte 1[2] 1[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_dtr_dce2 l_dtr_dce2 [2] [1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_rxd2[2] l_rxd2[1] pull pull sw_pad_ct VCC l_cspi2_ss 1[8] GND GND GND GND NVCC5 I pull pull sw_pad_ct VCC sw_pad_ct GND l_cspi2_ss l_cspi2_ss 2[8] 2[3] VCC VCC NVCC5 I pull pull sw_pad_ct VCC sw_pad_ct GND sw_pad_ct VCC l_cspi2_sc l_cspi2_sc l_cspi2_sc lk[8] lk[3] lk[4] pull sw_pad_ct VCC l_cspi2_sp i_rdy[8] pull sw_pad_ct VCC l_rxd1[8] pull sw_pad_ct VCC l_txd1[8] pull sw_pad_ct VCC l_rts1[8] pull sw_pad_ct VCC l_cts1[8] pull sw_pad_ct VCC l_dtr_dce1 [8] pull sw_pad_ct VCC l_dsr_dce 1[8] pull sw_pad_ct VCC l_ri_dce1[ 8] pull sw_pad_ct VCC l_dcd_dce 1[8] pull sw_pad_ct VCC l_dtr_dte1[ 8] pull sw_pad_ct VCC l_dsr_dte1 [8] GND GND GND NVCC5 I pull GND NVCC5 I pull pull pull pull pull GND GND GND GND GND GND GND GND NVCC8 I I I I I i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor GND sw_pad_ct GND NVCC8 l_txd1[4] GND GND GND GND GND GND GND NVCC8 GND NVCC8 GND NVCC8 Preliminary DSR_DCE1 GND pull GND GND sw_pad_ct GND NVCC8 l_dsr_dce 1[4] GND GND GND NVCC8 I RI_DCE1 GND pull GND I DCD_DCE1 GND pull GND GND GND GND NVCC8 I DTR_DTE1 GND pull GND GND VCC VCC NVCC8 I DSR_DTE1 GND pull GND GND GND GND NVCC8 I RI_DTE1 GND pull pull sw_pad_ct VCC sw_pad_ct GND l_ri_dte1[8 l_ri_dte1[3 ] ] pull sw_pad_ct VCC sw_pad_ct GND l_dcd_dte l_dcd_dte 1[8] 1[3] pull sw_pad_ct VCC l_dtr_dce2 [8] pull sw_pad_ct VCC l_rxd2[8] GND GND VCC VCC NVCC8 I DCD_DTE1 GND pull GND GND NVCC8 I DTR_DCE2 GND pull GND GND NVCC8 I RXD2 GND pull GND GND GND GND NVCC8 I Table 6. Pad Settings (continued) Pin Name Pad Slew Rate Loopback Drive Strength Enable (Max) Drive Strength Enable0 (High/ Normal) Pull Value Pull/ Keep Select Pull/ Keep Enable Open Drain Supply Schmitt Trigger Group Value After Reset Freescale Semiconductor i.MX31/i.MX31L Advance Information, Rev. 1.4 49 Preliminary TXD2 RTS2 CTS2 BATT_LINE regular sw_pad_ct slow l_txd2[0] regular sw_pad_ct slow l_rts2[0] regular sw_pad_ct slow l_cts2[0] regular slow slow GND GND GND VCC GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_txd2[2] l_txd2[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_rts2[2] l_rts2[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_cts2[2] l_cts2[1] VCC GND GND GND GND pu100 pu100 pull pull pull pull pull sw_pad_ct VCC l_txd2[8] pull sw_pad_ct VCC l_rts2[8] pull sw_pad_ct VCC l_cts2[8] pull sw_pad_ct VCC l_batt_line[ 8] pull sw_pad_ct VCC l_key_row 0[8] pull sw_pad_ct VCC l_key_row 1[8] pull sw_pad_ct VCC l_key_row 2[8] pull sw_pad_ct VCC l_key_row 3[8] pull sw_pad_ct VCC l_key_row 4[8] pull sw_pad_ct VCC l_key_row 5[8] pull sw_pad_ct VCC l_key_row 6[8] pull sw_pad_ct VCC l_key_row 7[8] GND GND GND VCC GND GND GND VCC GND GND GND GND GND NVCC8 GND NVCC8 GND NVCC8 GND NVCC5 I I I I KEY_ROW0 regular sw_pad_ct slow l_key_row 0[0] regular sw_pad_ct slow l_key_row 1[0] regular sw_pad_ct slow l_key_row 2[0] regular sw_pad_ct slow l_key_row 3[0] regular sw_pad_ct slow l_key_row 4[0] regular sw_pad_ct slow l_key_row 5[0] regular sw_pad_ct slow l_key_row 6[0] regular sw_pad_ct slow l_key_row 7[0] regular sw_pad_ct slow l_key_col0 [0] regular sw_pad_ct slow l_key_col1 [0] regular sw_pad_ct slow l_key_col2 [0] regular sw_pad_ct slow l_key_col3 [0] regular sw_pad_ct slow l_key_col4 [0] GND GND GND GND GND GND pu100 pu100 pull GND GND GND GND NVCC6 H KEY_ROW1 GND GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_key_row l_key_row 1[2] 1[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_key_row l_key_row 2[2] 2[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_key_row l_key_row 3[2] 3[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_key_row l_key_row 4[2] 4[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_key_row l_key_row 5[2] 5[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_key_row l_key_row 6[2] 6[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_key_row l_key_row 7[2] 7[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_key_col0 l_key_col0 [2] [1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_key_col1 l_key_col1 [2] [1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_key_col2 l_key_col2 [2] [1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_key_col3 l_key_col3 [2] [1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_key_col4 l_key_col4 [2] [1] pull GND GND GND GND NVCC6 H KEY_ROW2 GND pull GND GND GND GND NVCC6 H KEY_ROW3 GND pull GND GND GND GND NVCC6 H KEY_ROW4 GND pull GND GND GND GND NVCC6 H KEY_ROW5 GND pull GND GND GND GND NVCC6 H KEY_ROW6 GND pull GND GND GND GND NVCC6 H KEY_ROW7 GND pull GND GND GND GND NVCC6 H KEY_COL0 GND pull pull sw_pad_ct VCC ipp_ode_c GND l_key_col0 ol[0] [8] pull sw_pad_ct VCC ipp_ode_c GND l_key_col1 ol[1] [8] pull sw_pad_ct VCC ipp_ode_c GND l_key_col2 ol[2] [8] pull sw_pad_ct VCC ipp_ode_c GND l_key_col3 ol[3] [8] pull sw_pad_ct VCC ipp_ode_c GND ol[4] l_key_col4 [8] GND GND NVCC6 I KEY_COL1 GND pull GND GND NVCC6 I KEY_COL2 GND pull GND GND NVCC6 I Signal Descriptions KEY_COL3 GND pull GND GND NVCC6 I KEY_COL4 GND pull GND GND NVCC6 I Table 6. Pad Settings (continued) Pin Name Pad Slew Rate Loopback Drive Strength Enable (Max) Drive Strength Enable0 (High/ Normal) Pull Value Pull/ Keep Select Pull/ Keep Enable Open Drain Supply Schmitt Trigger Group Value After Reset 50 KEY_COL5 regular sw_pad_ct slow l_key_col5 [0] regular sw_pad_ct slow l_key_col6 [0] regular sw_pad_ct slow l_key_col7 [0] regular regular regular regular regular regular regular fast slow slow slow fast slow slow fast slow slow slow fast slow slow GND KEY_COL6 GND KEY_COL7 GND RTCK TCK TMS TDI TDO TRSTB DE SJC_MOD GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Signal Descriptions GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_key_col5 l_key_col5 [2] [1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_key_col6 l_key_col6 [2] [1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_key_col7 l_key_col7 [2] [1] GND GND GND GND GND GND GND VCC GND GND GND VCC GND GND VCC pd100 pd100 GND pd100 pd100 GND pu100 pu100 GND pu100 pu100 VCC pu100 pu100 GND pu100 pu100 GND pu100 pu100 pull pull sw_pad_ct VCC ipp_ode_c GND l_key_col5 ol[5] [8] pull sw_pad_ct VCC ipp_ode_c GND l_key_col6 ol[6] [8] pull sw_pad_ct VCC ipp_ode_c GND l_key_col7 ol[7] [8] pull pull pull pull pull pull pull pull GND VCC VCC VCC GND VCC VCC VCC GND VCC VCC VCC GND VCC VCC VCC GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND NVCC6 I pull GND GND NVCC6 I pull GND GND NVCC6 I pull pull pull pull pull pull pull pull GND VCC VCC VCC GND GND GND GND GND NVCC6 VCC VCC VCC NVCC6 NVCC6 NVCC6 I I I I L I I I i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor GND NVCC6 GND NVCC6 GND NVCC6 GND NVCC6 regular sw_pad_ct slow l_sjc_mod [0] regular sw_pad_ct slow l_usb_pwr [0] regular sw_pad_ct slow l_usb_oc [0] regular sw_pad_ct slow l_usb_byp[ 0] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_sjc_mod l_sjc_mod [2] [1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_usb_pwr l_usb_pwr [2] [1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_usb_oc l_usb_oc [2] [1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_usb_byp[ l_usb_byp[ 2] 1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_usbotg_c l_usbotg_c lk[2] lk[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_usbotg_ l_usbotg_ dir[2] dir[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_usbotg_s l_usbotg_s tp[2] tp[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_usbotg_ l_usbotg_ nxt[2] nxt[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_usbotg_ l_usbotg_ data0[2] data0[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_usbotg_ l_usbotg_ data1[2] data1[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_usbotg_ l_usbotg_ data2[2] data2[1] Preliminary USB_PWR GND pull pull sw_pad_ct VCC l_usb_pwr [8] pull sw_pad_ct VCC l_usb_oc [8] pull sw_pad_ct VCC l_usb_byp[ 8] pull sw_pad_ct VCC l_usbotg_c lk[8] pull sw_pad_ct VCC l_usbotg_ dir[8] pull sw_pad_ct VCC l_usbotg_s tp[8] pull sw_pad_ct VCC l_usbotg_ nxt[8] pull sw_pad_ct VCC l_usbotg_ data0[8] pull sw_pad_ct VCC l_usbotg_ data1[8] pull sw_pad_ct VCC l_usbotg_ data2[8] GND GND GND GND NVCC5 I USB_OC GND pull GND GND GND GND NVCC5 I USB_BYP GND pull GND GND GND GND NVCC5 I USBOTG_CLK regular sw_pad_ct slow l_usbotg_c lk[0] USBOTG_DIR regular sw_pad_ct slow l_usbotg_ dir[0] USBOTG_STP regular sw_pad_ct slow l_usbotg_s tp[0] USBOTG_NXT regular sw_pad_ct slow l_usbotg_ nxt[0] USBOTG_DAT regular sw_pad_ct slow A0 l_usbotg_ data0[0] USBOTG_DAT regular sw_pad_ct slow A1 l_usbotg_ data1[0] USBOTG_DAT regular sw_pad_ct slow A2 l_usbotg_ data2[0] GND pull GND GND sw_pad_ct VCC l_usbotg_c lk[4] GND GND NVCC5 I GND pull GND GND NVCC5 I GND pull GND GND GND GND NVCC5 I GND pull GND GND GND GND NVCC5 I GND pull GND GND GND GND NVCC5 I GND pull GND GND GND GND NVCC5 I GND pull GND GND GND GND NVCC5 I Table 6. Pad Settings (continued) Pin Name Pad Slew Rate Loopback Drive Strength Enable (Max) Drive Strength Enable0 (High/ Normal) Pull Value Pull/ Keep Select Pull/ Keep Enable Open Drain Supply Schmitt Trigger Group Value After Reset Freescale Semiconductor i.MX31/i.MX31L Advance Information, Rev. 1.4 51 Preliminary USBOTG_DAT regular sw_pad_ct slow A3 l_usbotg_ data3[0] USBOTG_DAT regular sw_pad_ct slow A4 l_usbotg_ data4[0] USBOTG_DAT regular sw_pad_ct slow A5 l_usbotg_ data5[0] USBOTG_DAT regular sw_pad_ct slow A6 l_usbotg_ data6[0] USBOTG_DAT regular sw_pad_ct slow A7 l_usbotg_ data7[0] USBH2_CLK regular sw_pad_ct slow l_usbh2_cl k[0] USBH2_DIR regular sw_pad_ct slow l_usbh2_di r[0] USBH2_STP regular sw_pad_ct slow l_usbh2_st p[0] USBH2_NXT regular sw_pad_ct slow l_usbh2_n xt[0] USBH2_DATA0 regular sw_pad_ct slow l_usbh2_d ata0[0] USBH2_DATA1 regular sw_pad_ct slow l_usbh2_d ata1[0] LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 regular regular regular regular regular regular regular regular fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast GND GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_usbotg_ l_usbotg_ data3[2] data3[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_usbotg_ l_usbotg_ data4[2] data4[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_usbotg_ l_usbotg_ data5[2] data5[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_usbotg_ l_usbotg_ data6[2] data6[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_usbotg_ l_usbotg_ data7[2] data7[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_usbh2_cl l_usbh2_cl k[2] k[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_usbh2_di l_usbh2_di r[2] r[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_usbh2_st l_usbh2_st p[2] p[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_usbh2_n l_usbh2_n xt[2] xt[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_usbh2_d l_usbh2_d ata0[2] ata0[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_usbh2_d l_usbh2_d ata1[2] ata1[1] GND sw_pad_ct GND l_ld0[2] GND sw_pad_ct GND l_ld1[2] GND sw_pad_ct GND l_ld2[2] GND sw_pad_ct GND l_ld3[2] GND sw_pad_ct GND l_ld4[2] GND sw_pad_ct GND l_ld5[2] GND sw_pad_ct GND l_ld6[2] GND sw_pad_ct GND l_ld7[2] VCC VCC VCC VCC VCC VCC VCC VCC pull pull sw_pad_ct VCC l_usbotg_ data3[8] pull sw_pad_ct VCC l_usbotg_ data4[8] pull sw_pad_ct VCC l_usbotg_ data5[8] pull sw_pad_ct VCC l_usbotg_ data6[8] pull sw_pad_ct VCC l_usbotg_ data7[8] pull sw_pad_ct VCC l_usbh2_cl k[8] pull sw_pad_ct VCC l_usbh2_di r[8] pull sw_pad_ct VCC l_usbh2_st p[8] pull sw_pad_ct VCC l_usbh2_n xt[8] pull sw_pad_ct VCC l_usbh2_d ata0[8] pull sw_pad_ct VCC l_usbh2_d ata1[8] VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC GND GND GND GND NVCC5 I GND pull GND GND GND GND NVCC5 I GND pull GND GND GND GND NVCC5 I GND pull GND GND GND GND NVCC5 I GND pull GND GND GND GND NVCC5 I GND pull GND GND sw_pad_ct VCC NVCC10 l_usbh2_cl k[4] GND GND GND NVCC10 I GND pull GND I GND pull GND GND GND GND NVCC10 I GND pull GND GND GND GND NVCC10 I GND pull GND GND GND GND NVCC10 I GND pull GND GND GND GND NVCC10 I GND GND GND GND GND GND GND GND VCC pu100 pu100 sw_pad_ct pull l_ld0[7] VCC pu100 pu100 sw_pad_ct pull l_ld1[7] VCC pu100 pu100 sw_pad_ct pull l_ld2[7] VCC pu100 pu100 sw_pad_ct pull l_ld3[7] VCC pu100 pu100 sw_pad_ct pull l_ld4[7] VCC pu100 pu100 sw_pad_ct pull l_ld5[7] VCC pu100 pu100 sw_pad_ct pull l_ld6[7] VCC pu100 pu100 sw_pad_ct pull l_ld7[7] GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND NVCC7 GND NVCC7 GND NVCC7 GND NVCC7 GND NVCC7 GND NVCC7 GND NVCC7 GND NVCC7 I I I I I I I I Signal Descriptions Table 6. Pad Settings (continued) Pin Name Pad Slew Rate Loopback Drive Strength Enable (Max) Drive Strength Enable0 (High/ Normal) Pull Value Pull/ Keep Select Pull/ Keep Enable Open Drain Supply Schmitt Trigger Group Value After Reset 52 LD8 LD9 LD10 LD11 LD12 LD13 regular regular regular regular regular regular regular regular regular regular regular fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast fast GND GND GND GND GND GND GND GND GND GND GND Signal Descriptions GND sw_pad_ct GND l_ld8[2] GND sw_pad_ct GND l_ld9[2] GND sw_pad_ct GND l_ld10[2] GND sw_pad_ct GND l_ld11[2] GND sw_pad_ct GND l_ld12[2] GND sw_pad_ct GND l_ld13[2] GND sw_pad_ct GND l_ld14[2] GND sw_pad_ct GND l_ld15[2] GND sw_pad_ct GND l_ld16[2] GND sw_pad_ct GND l_ld17[2] GND sw_pad_ct GND l_vsync0 [2] GND sw_pad_ct GND l_hsync[2] GND sw_pad_ct GND l_fpshift[2] GND sw_pad_ct GND l_drdy0[2] GND sw_pad_ct GND l_sd_d_i[2] GND sw_pad_ct GND l_sd_d_io [2] GND sw_pad_ct GND l_sd_d_clk [2] GND sw_pad_ct GND l_lcs0[2] GND sw_pad_ct GND l_lcs1[2] GND sw_pad_ct GND l_ser_rs[2] GND sw_pad_ct GND l_par_rs[2] GND sw_pad_ct GND l_write[2] VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC pu100 pu100 sw_pad_ct pull l_ld8[7] VCC pu100 pu100 sw_pad_ct pull l_ld9[7] VCC pu100 pu100 sw_pad_ct pull l_ld10[7] VCC pu100 pu100 sw_pad_ct pull l_ld11[7] VCC pu100 pu100 sw_pad_ct pull l_ld12[7] VCC pu100 pu100 sw_pad_ct pull l_ld13[7] VCC pu100 pu100 sw_pad_ct pull l_ld14[7] VCC pu100 pu100 sw_pad_ct pull l_ld15[7] VCC pu100 pu100 sw_pad_ct pull l_ld16[7] VCC pu100 pu100 sw_pad_ct pull l_ld17[7] VCC pu100 pu100 sw_pad_ct pull l_vsync0 [7] VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 pull pull pull pull pull pull pull pull pull pull VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND NVCC7 GND NVCC7 GND NVCC7 GND NVCC7 GND NVCC7 GND NVCC7 GND NVCC7 GND NVCC7 GND NVCC7 GND NVCC7 GND NVCC7 I I I I I I I I I I I i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor LD14 LD15 LD16 LD17 VSYNC0 Preliminary HSYNC FPSHIFT DRDY0 SD_D_I SD_D_IO regular regular regular regular regular fast fast fast fast fast fast fast fast fast fast GND GND GND GND GND VCC VCC VCC VCC VCC GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND NVCC7 GND NVCC7 GND NVCC7 GND NVCC7 GND NVCC7 I I I I I SD_D_CLK regular fast fast GND VCC VCC pu100 pu100 pull pull GND GND GND GND GND GND NVCC7 I LCS0 LCS1 SER_RS PAR_RS WRITE regular regular regular regular regular fast fast fast fast fast fast fast fast fast fast GND GND GND GND GND VCC VCC VCC VCC VCC VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 VCC pu100 pu100 pull pull pull pull pull pull pull pull pull pull GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND NVCC7 GND NVCC7 GND NVCC7 GND NVCC7 GND NVCC7 I I I I I Table 6. Pad Settings (continued) Pin Name Pad Slew Rate Loopback Drive Strength Enable (Max) Drive Strength Enable0 (High/ Normal) Pull Value Pull/ Keep Select Pull/ Keep Enable Open Drain Supply Schmitt Trigger Group Value After Reset Freescale Semiconductor i.MX31/i.MX31L Advance Information, Rev. 1.4 53 Preliminary READ VSYNC3 regular regular fast fast fast fast GND GND GND sw_pad_ct GND l_read[2] GND sw_pad_ct GND l_vsync3 [2] GND sw_pad_ct GND l_contrast [2] GND sw_pad_ct GND l_d3_rev [2] GND sw_pad_ct GND l_d3_cls[2] GND sw_pad_ct GND l_d3_spl[2] VCC VCC VCC pu100 pu100 pull pull GND VCC GND VCC GND GND GND GND GND GND GND NVCC7 GND NVCC7 I I VCC pu100 pu100 sw_pad_ct pull l_vsync3 [7] VCC pu100 pu100 pull pull CONTRAST regular fast fast GND VCC GND GND GND GND GND GND NVCC7 I D3_REV regular fast fast GND VCC VCC pu100 pu100 pull pull GND GND GND GND GND GND NVCC7 I D3_CLS D3_SPL SD1_CMD regular regular fast fast fast fast GND GND VCC VCC VCC pu100 pu100 VCC pu100 pu100 pull pull pull pull pull pull GND GND GND GND GND GND GND GND GND GND GND GND GND GND NVCC7 GND NVCC7 I I I regular sw_pad_ct fast sw_pad_ct GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_sd1_cmd l_sd1_cmd l_sd1_cmd l_sd1_cmd [0] [9] [2] [1] regular sw_pad_ct fast l_sd1_clk [0] GND GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_sd1_clk l_sd1_clk[ [2] 1] GND sw_pad_ct GND NVCC3 l_sd1_cmd [4] GND GND GND NVCC3 SD1_CLK pull pull GND GND GND I SD1_DATA0 regular sw_pad_ct fast sw_pad_ct GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_sd1_dat l_sd1_dat l_sd1_dat l_sd1_dat a0[0] a0[9] a0[2] a0[1] regular sw_pad_ct fast sw_pad_ct GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_sd1_dat l_sd1_dat l_sd1_dat l_sd1_dat a1[0] a1[9] a1[2] a1[1] regular sw_pad_ct fast sw_pad_ct GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_sd1_dat l_sd1_dat l_sd1_dat l_sd1_dat a2[0] a2[9] a2[2] a2[1] regular sw_pad_ct fast sw_pad_ct GND sw_pad_ct GND sw_pad_ct GND pd100 pd100 l_sd1_dat l_sd1_dat l_sd1_dat l_sd1_dat a3[9] a3[2] a3[1] a3[0] regular sw_pad_ct slow l_ata_cs0 [0] regular sw_pad_ct slow l_ata_cs1 [0] regular sw_pad_ct slow l_ata_dior[ 0] regular sw_pad_ct slow l_ata_diow [0] GND GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_ata_cs0 l_ata_cs0 [2] [1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_ata_cs1 l_ata_cs1 [2] [1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_ata_dior[ l_ata_dior 2] [1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_ata_diow l_ata_diow [2] [1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_ata_dma l_ata_dma ck[2] ck[1] pull pull sw_pad_ct GND l_sd1_dat a0[8] pull sw_pad_ct GND l_sd1_dat a1[8] pull sw_pad_ct GND l_sd1_dat a2[8] pull sw_pad_ct GND l_sd1_dat a3[8] pull GND GND GND GND GND GND NVCC3 I SD1_DATA1 pull GND GND GND GND NVCC3 I SD1_DATA2 pull GND GND GND GND NVCC3 I SD1_DATA3 pull GND GND GND GND NVCC3 I ATA_CS0 pull GND GND GND GND NVCC3 I ATA_CS1 GND pull pull GND GND GND GND GND GND NVCC3 I ATA_DIOR GND pull pull sw_pad_ct VCC l_ata_dior[ 8] pull sw_pad_ct VCC l_ata_diow [8] pull sw_pad_ct VCC l_ata_dma ck[8] GND GND GND GND NVCC3 I Signal Descriptions ATA_DIOW GND pull GND GND GND GND NVCC3 I ATA_DMACK regular sw_pad_ct slow l_ata_dma ck[0] GND pull GND GND GND GND NVCC3 I Table 6. Pad Settings (continued) Pin Name Pad Slew Rate Loopback Drive Strength Enable (Max) Drive Strength Enable0 (High/ Normal) Pull Value Pull/ Keep Select Pull/ Keep Enable Open Drain Supply Schmitt Trigger Group Value After Reset 54 ATA_RESET regular sw_pad_ct slow l_ata_rese t_b[0] CE_CONTROL regular CLKSS regular fast fast fast fast GND GND GND GND GND GND GND GND CSPI3_MOSI regular sw_pad_ct slow l_cspi3_m osi[0] CSPI3_MISO regular sw_pad_ct slow l_cspi3_mi so[0] CSPI3_SCLK regular sw_pad_ct slow l_cspi3_sc lk[0] CSPI3_SPI_R regular sw_pad_ct slow DY l_cspi3_sp i_rdy[0] TTM_PAD IOQVDD MVCC MGND UVCC UGND FVCC FGND SVCC SGND NVCC1 NVCC2 NVCC3 NVCC4 NVCC5 NVCC6 NVCC7 NVCC8 NVCC9 NVCC10 NVCC10 NVCC21 NVCC22 NGND1 regular - - - - - - - - - - - - - - - - - - - - - - - slow - - - - - - - - - - - - - - - - - - - - - - - slow - - - - - - - - - - - - - - - - - - - - - - - GND GND Signal Descriptions GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_ata_rese l_ata_rese t_b[2] t_b[1] GND GND GND GND GND pd100 pd100 GND pu100 pu100 pull pull sw_pad_ct VCC l_ata_rese t_b[8] pull pull GND GND GND GND GND GND GND GND NVCC3 I pull pull pull GND GND GND GND GND GND GND GND GND GND NVCC8 GND NVCC1 GND NVCC3 I I I GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_cspi3_m l_cspi3_m osi[2] osi[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_cspi3_mi l_cspi3_mi so[2] so[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_cspi3_sc l_cspi3_sc lk[2] lk[1] GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 l_cspi3_sp l_cspi3_sp i_rdy[1] i_rdy[2] GND - - - - - - - - - - - - - - - - - - - - - - - GND - - - - - - - - - - - - - - - - - - - - - - - GND - - - - - - - - - - - - - - - - - - - - - - - GND - - - - - - - - - - - - - - - - - - - - - - - GND pu100 pu100 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - pull sw_pad_ct VCC l_cspi3_m osi[8] pull sw_pad_ct VCC l_cspi3_mi so[8] pull sw_pad_ct VCC l_cspi3_sc lk[8] pull sw_pad_ct VCC l_cspi3_sp i_rdy[8] pull - - - - - - - - - - - - - - - - - - - - - - - GND - - - - - - - - - - - - - - - - - - - - - - - GND - - - - - - - - - - - - - - - - - - - - - - - pull GND GND GND GND NVCC3 I pull GND GND sw_pad_ct VCC l_cspi3_sc lk[4] GND GND NVCC3 I i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor GND pull GND GND NVCC3 I GND - - - - - - - - - - - - - - - - - - - - - - - pull - - - - - - - - - - - - - - - - - - - - - - - GND - - - - - - - - - - - - - - - - - - - - - - - GND - - - - - - - - - - - - - - - - - - - - - - - GND - - - - - - - - - - - - - - - - - - - - - - - GND NVCC7 - - - - - - - - - - - - - - - - - - - - - - - NVCC22 mvcc_vd di mvcc_vd di NVCC7 NVCC7 NVCC2 NVCC2 svcc_vd di svcc_vd di - - - - - - - - - - - - - - NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA Preliminary Table 6. Pad Settings (continued) Pin Name Pad Slew Rate Loopback Drive Strength Enable (Max) Drive Strength Enable0 (High/ Normal) Pull Value Pull/ Keep Select Pull/ Keep Enable Open Drain Supply Schmitt Trigger Group Value After Reset Freescale Semiconductor i.MX31/i.MX31L Advance Information, Rev. 1.4 55 Preliminary NGND2 NGND3 NGND4 NGND5 NGND6 NGND7 NGND8 NGND9 NGND10 NGND21 NGND22 QVCC QVCC1 QVCC4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - NA NA NA NA NA NA NA NA NA NA NA NA NA NA Signal Descriptions Signal Descriptions 3.1.3 EMI Pins Multiplexing This section discusses the multiplexing of EMI signals. The EMI signals' multiplexing is done inside the EMI. Table 7 lists the i.MX31 and i.MX31L pin names, pad types, and the memory devices' equivalent pin names. Table 7. EMI Multiplexing Pin Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 MA10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 SDBA1 SDBA0 Pad Type regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular WEIM A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 - A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 SDBA1 SDBA0 SDRAM MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 - MA10 MA11 MA12 MA13 - - - - - - - - - - - - - - PCMCIA A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 - A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 CE1 CE2 DDR MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 - MA10 MA11 MA12 MA13 - - - - - - - - - - - - - - NFC - - - - - - - - - - - - - - - - - - - - - - - - - - - - - i.MX31/i.MX31L Advance Information, Rev. 1.4 56 Preliminary Freescale Semiconductor Signal Descriptions Table 7. EMI Multiplexing (continued) Pin Name SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 SD16 SD17 SD18 SD19 SD20 SD21 SD22 SD23 SD24 SD25 SD26 SD27 SD28 SD29 SD30 SD31 DQM0 Pad Type ddr ddr ddr ddr ddr ddr ddr ddr ddr ddr ddr ddr ddr ddr ddr ddr ddr ddr ddr ddr ddr ddr ddr ddr ddr ddr ddr ddr ddr ddr ddr ddr ddr WEIM - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SDRAM SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 SD16 SD17 SD18 SD19 SD20 SD21 SD22 SD23 SD24 SD25 SD26 SD27 SD28 SD29 SD30 SD31 DQM0 PCMCIA - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - DDR - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - NFC - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 57 Signal Descriptions Table 7. EMI Multiplexing (continued) Pin Name DQM1 DQM2 DQM3 EB0 EB1 OE CS0 CS1 CS2 CS3 CS4 CS5 ECB LBA BCLK RW RAS CAS SDWE SDCKE0 SDCKE1 SDCLK SDCLK SDQS0 SDQS1 SDQS2 SDQS3 NFWE NFRE NFALE NFCLE NFWP NFCE Pad Type ddr ddr ddr regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular ddr ddr ddr ddr ddr ddr regular regular regular regular regular regular WEIM - - - EB0 EB1 OE CS0 CS1 CS2 CS3 CS4 CS5 ECB LBA BCLK RW - - - - - - - - - - - - - - - - - SDRAM DQM1 DQM2 DQM3 - - - - - CSD0 CSD1 - - - - - - RAS CAS SDWE SDCKE0 SDCKE1 SDCLK SDCLK - - - - - - - - - - PCMCIA - - - REG IORD IOWR - - - - - - - OE - WE - - - - - - - - - - - - - - - - - DDR - - - - - - - - - - - - - - - - - - - - - - - SDQS0 SDQS1 SDQS2 SDQS3 - - - - - - NFC - - - - - - - - - - - - - - - - - - - - - - - - - - - WE RE ALE CLE WP CE i.MX31/i.MX31L Advance Information, Rev. 1.4 58 Preliminary Freescale Semiconductor Signal Descriptions Table 7. EMI Multiplexing (continued) Pin Name NFRB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PC_CD1 PC_CD2 PC_WAIT PC_READY PC_PWRON PC_VS1 PC_VS2 PC_BVD1 PC_BVD2 PC_RST IOIS16 PC_RW PC_POE M_REQUEST M_GRANT Pad Type regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular regular WEIM - D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 - - - - - - - - - - - - - - - SDRAM - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PCMCIA - D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CD1 CD2 WAIT READY PC_PWRON VS1 VS2 BVD1 BVD2 RST IOIS16/WP RW POE - - DDR - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - NFC R/B D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 - - - - - - - - - - - - - - - i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 59 Electrical Characteristics 4 Electrical Characteristics This section provides the chip-level and module-level electrical characteristics for the i.MX31 and i.MX31L: * Section 4.1, "i.MX31 and i.MX31L Chip-Level Conditions" on page 60 -- Section 4.1.1, "Power Specifications" on page 63 * Section 4.2, "Supply Power-Up Requirements and Restrictions" on page 66 * Section 4.3, "Module-Level Electrical Specifications" on page 66 -- Section 4.3.1, "I/O Pad (PADIO) Electrical Specifications" on page 66 -- Section 4.3.3, "Clock Amplifier Module (CAMP) Electrical Characteristics" on page 70 -- Section 4.3.4, "1-Wire Electrical Specifications" on page 70 -- Section 4.3.5, "ATA Electrical Specifications (ATA Bus, Bus Buffers)" on page 72 -- Section 4.3.6, "AUDMUX Electrical Specifications" on page 80 -- Section 4.3.7, "CSPI Electrical Specifications" on page 80 -- Section 4.3.8, "DPLL Electrical Specifications" on page 82 -- Section 4.3.9, "EMI Electrical Specifications" on page 83 - Section 4.3.9.1, "NAND Flash Controller Interface (NFC)" on page 83 - Section 4.3.9.2, "Wireless External Interface Module (WEIM)" on page 88 - Section 4.3.9.3, "SDRAM (DDR and SDR) Memory Controller" on page 93 -- Section 4.3.11, "FIR Electrical Specifications" on page 101 -- Section 4.3.12, "Fusebox Electrical Specifications" on page 101 -- Section 4.3.13, "I2C Electrical Specifications" on page 102 -- Section 4.3.14, "IPU--Sensor Interfaces" on page 106 -- Section 4.3.15, "IPU--Display Interfaces" on page 106 -- Section 4.3.16, "Memory Stick Host Controller (MSHC)" on page 131 -- Section 4.3.17, "Personal Computer Memory Card International Association (PCMCIA)" on page 133 -- Section 4.3.18, "PWM Electrical Specifications" on page 135 -- Section 4.3.19, "SDHC Electrical Specifications" on page 137 -- Section 4.3.20, "SIM Electrical Specifications" on page 138 -- Section 4.3.21, "SJC Electrical Specifications" on page 141 -- Section 4.3.22, "SSI Electrical Specifications" on page 143 -- Section 4.3.23, "USB Electrical Specifications" on page 151 4.1 i.MX31 and i.MX31L Chip-Level Conditions This section provides the chip-level electrical characteristics for the IC. See Table 8 for a quick reference to the individual tables and sections. i.MX31/i.MX31L Advance Information, Rev. 1.4 60 Preliminary Freescale Semiconductor Electrical Characteristics Table 8. i.MX31/i.MX31L Chip-Level Conditions For these characteristics, ... Table 9, "DC Recommended Operating Conditions" Table 10, "Voltage versus Core Frequency" Table 11, "Interface Frequency" Table 12, "DC Absolute Maximum Operating Conditions" Section 4.1.1, "Power Specifications" Topic appears ... on page 61 on page 62 on page 62 on page 63 on page 63 Table 9 provides the DC recommended operating conditions. NOTE The use of the terms OVDD and OVSS in this section refers to VDD/VSS Power rails of I/O pads, which are supplied by the nearest noisy (VDDIOL/H and VDD_DDR) supply pads, and are in the range of 1.75 to 3.1 V. Table 9. DC Recommended Operating Conditions ID 1 2 3 4 5 6 7 8 9 1 2 Parameter Core Supply Voltage1, 2 (QVCC, QVCC1, QVCC4) State Retention (SR) Operating Voltage4 I/O Supply Voltage NVCC1, NVCC3, NVCC4-10 I/O Supply Voltage NVCC1, NVCC3, NVCC4-10 Supply Voltage (DDR Output Drive Supply) NVCC2, NVCC21, NVCC22 PLL/FPM supplies: FVCC, MVCC, SVCC, UVCC9 Fusebox read Supply Voltage on the VDD_FUSE pin Fusebox Program Supply Voltage on the VDD_FUSE pin Operating Ambient Temperature 10 Symbol VDD VSR VDDIOL VDDIOH VDD_DDR VPLL VFUSE VFUSE_PGM TA Min 1.22 0.95 1.75 2.75 1.75 1.3 1.65 3.0 0 Max 1.653 - 1.9 3.16,7,8 1.95 1.6 1.95 3.3 70 Units V V V V V V V V o C Measured at supply pins, including peripherals, ARM, and L2 cache supplies (QVCC, QVCC1, QVCC4, respectively). Min voltage listed is for the lower frequency. See Table 10 for correlation of voltage range and associated frequencies. 3 Core voltage supply is considered "Overdrive" for 1.45-1.65 V range. Duty cycles in core overdrive--whether switching or not--must be limited to a cumulative duration of 1.25 years or less (25% duty cycle for a 5-year rated part) to sustain a maximum core VDD operating voltage of 1.65 V without significant device degradation. 4 The SR voltage (Quiet supplies QVCC, QVCC1, QVCC4), is applied after IC is put in SR mode. NOTE: Applying low voltage point is dependent on noisy (NVCC) supplies being less than or equal to 1.95 V. 5 The range--1.9 V to 2.7 V--is a valid voltage range; however, the voltage ranges given in this table align to more common industry voltage ranges. i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 61 Electrical Characteristics 6 Recommended maximum OVDD operating voltage is 3.1 V for GPIO in either slow or fast mode. Switching duty cycles must be limited to a cumulative duration of 1 year or less (20% duty cycle for a 5yr rated part) to sustain a MAX OVDD operating voltage of 3.3V without significant device degradation. A switching cycle is defined as the period of time that the pad is powered to OVDD and actively switching. Switching cycles exceeding this limit may affect device performance or cause permanent damage to the device. 7 The performance at 1.8 V of GPIO devices that are operated at 3.3 V over an extended period of time (for example. 2 years or longer at a 20% duty cycle) is not guaranteed. Reliability degradation may render the device too slow or inoperable. 8 Overshoot and undershoot conditions (transitions above OVDD and below OVSS) on switching pads must be held below 0.6 V, and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/undershoot must be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device. 9 For normal operating conditions, PLLs' and core supplies must maintain the following relation: PLL Core - 100 mV. In other words, for a 1.6 V core supply, PLL supplies must be set to 1.5 V or higher. 10 Providing a voltage that is lower than specified does not prevent the fuses from being blown if attempting to program a fuse. Table 10 gives details of the applied voltages to the i.MX31/i.MX31L Core Supply I/O versus the frequencies of the ARM11 core. Table 10. Voltage versus Core Frequency ID 1 2 1 2 Core ARM11 (VDD) Symbol fARM fARM Min (V) 1.221 1.553 Max (V) 1.651, 2 1.653 Frequency (MHz) 0-400 401-532 As measured at the ball. Recommended settings for PMIC (Power Management IC) is 1.275 V. All overdrive/25% duty-cycles restrictions apply, as specified in Table 9. 3 As measured at the ball. Recommended voltage settings for PMIC is 1.6 V. Table 11 provides information for interface frequency limits. For more details about clocks characteristics, see Section 4.3.8, "DPLL Electrical Specifications" on page 82. Table 11. Interface Frequency ID 1 2 3 Parameter JTAG TCK Frequency CKIL Frequency CKIH Frequency Symbol fJTAG fCKIL fCKIH Min DC 32 10 Typ 5 32.768 26 Max 10 38.4 100 Units MHz kHz MHz Table 12 provides the DC absolute maximum operating conditions. CAUTION Stresses beyond those listed under "DC Absolute Maximum Operating Conditions," (Table 12) may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. i.MX31/i.MX31L Advance Information, Rev. 1.4 62 Preliminary Freescale Semiconductor Electrical Characteristics Table 12. DC Absolute Maximum Operating Conditions Ref. Num 1 2 3 4 5 6 1 Parameter Supply Voltage Supply Voltage (Level Shift I/O) Input Voltage Range Storage Temperature Absolute Maximum HBM (Human Body Model) ESD stress voltage. Absolute Maximum offset voltage allowed in run mode between core supplies. Symbol VDDmax VDDIOmax VImax Tstorage Vesd Vcoers_offset1 Min -0.5 -0.5 -0.5 -40 - - Max 1.65 3.3 VDDIOH +0.3 125 Units V V V oC 2500 +15 V mV The offset is any difference between all core voltages for supply pads--QVCC, QVCC1, and QVCC4. 4.1.1 Power Specifications Table 13 shows the power consumption for the i.MX31 and i.MX31L. i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 63 Electrical Characteristics Table 13. Power Consumption (Typical Values) Mode State Retention * * * * * * * * * * * * * * * * * * * * * * * * * * Conditions Core VDD (QVCC) = 0.95 V ARM supply QVCC1 = QVCC = 0.95 V ARM in well bias L2 caches are power gated (QVCC4 = 0 V) All PLLs are Off FPM is off 32 kHz Input on CKIH input is off CAMP is off TCK input is off All the modules are off No external resistive loads RNGA oscillator is off TA = 25C Peripheral Current1 200 A ARM PLL Total Power Current2 Current 150 A 40 A 0.4 mW Doze All Vdds = 1.2 V (QVCC=QVCC1= QVCC4 = 1.2 V) ARM in wait for interrupt mode ARM is in well bias MAX is stopped L2 cache is stopped but powered MCU PLL is on (532 MHz) USB PLL and SPLL are off FPM is on CKIH input is off CAMP is off 32 kHz Input on All the modules are off (by programming CGR[2:0] registers) * RNGA oscillator is off * No external resistive loads * TA = 25C 7 mA 1.0 mA 3 mA for each PLL 13.0 mW i.MX31/i.MX31L Advance Information, Rev. 1.4 64 Preliminary Freescale Semiconductor Electrical Characteristics Table 13. Power Consumption (Typical Values) (continued) Mode WAIT (all clocks gated off) * * * * * * * * * * * Conditions All Vdds = 1.2 V (QVCC=QVCC1=QVCC4 = 1.2 V) ARM in wait for interrupt mode MAX is active L2 cache is stopped but powered MCU PLL is on (532 MHz) USB PLL and SPLL are off FPM is on CKIH input is off CAMP is off 32 kHz Input on All the modules are off (by programming CGR[2:0] registers) * RNGA oscillator is off * No external resistive loads * TA = 25C * * * * * * * * * * * * Core VDD (QVCC) = 0.95 V ARM (QVCC1) & L2 caches (QVCC4) are power gate All PLLs are off FPM is off 32 kHz Input on CKIH input is off CAMP is off TCK input is off All the modules are off No external resistive loads RNGA oscillator is off TA = 25C Peripheral Current1 7 mA ARM PLL Total Power Current2 Current 3 mA 3 mA for each PLL 15.0 mW Deep Sleep 200 A 0 A 40 A 0.22 mW 1 2 QVCC supply. QVCC1 supply. 4.2 Supply Power-Up Requirements and Restrictions Any i.MX31/i.MX31L board design must comply with the power-up sequence guideline, as described in this section, to guarantee proper power-up of the device. Any deviation from this sequence may result in any or all of the following situations: * Cause excessive current. * Prevent the device from booting. * Cause irreversible damage to the i.MX31/i.MX31L (worst-case scenario). The Power On Reset (POR) pin must be kept asserted (low) throughout the power up sequence. Power up logic must guarantee that all power sources must be on prior to the release (de-assertion) of POR. Figure 2 depicts the power supply power up sequence. (Power management logic should guarantee 90% supply before transitional to the next state.) The sequence is as follows: 1. Quiet supplies--QVCC, QVCC1, QVCC4 (peripherals, ARM, L2 cache) 2. NVCC1 and IOQVDD--for assuring reset signals are propagating into core i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 65 Electrical Characteristics 3. Powering up of the remainder of noisy and PLL supplies, which can be done simultaneously. The order within the noisy supplies must be maintained, as follows: a) Remainder of noisy supplies (all except for the NVCC2, 21,22, and NVCC1 supplies) b) NVCC2, NVCC21, NVCC22. 4. FUSE_VDD--the last supply to be powered up Hold POR Asserted QVCC, QVCC1, QVCC4 NVCC1, IOQVDD PLL's Supplies Remainder of Noisy Supplies-- VDDIOL/H NVCC2, NVCC21, 22 FUSE_VDD Release POR Figure 2. Power-Up Sequence 4.3 Module-Level Electrical Specifications This section contains the i.MX31 and i.MX31L electrical information including timing specifications, arranged in alphabetical order by module name. 4.3.1 I/O Pad (PADIO) Electrical Specifications This section specifies the AC/DC characterization of functional I/O pads of the i.MX31. There are two main types of pads: regular and DDR. In this document, the "Regular" type is referred to as GPIO. 4.3.1.1 DC Electrical Characteristics The i.MX31/i.MX31L pad I/O operating characteristics appear in Table 14 for GPIO pads and Table 15 for DDR (Double Data Rate) pads. i.MX31/i.MX31L Advance Information, Rev. 1.4 66 Preliminary Freescale Semiconductor Electrical Characteristics Table 14. GPIO Pads DC Electrical Parameters Parameter High-level output voltage Symbol VOH Test Conditions IOH = -1 mA IOH = spec'ed Drive Low-level output voltage VOL IOL = 1 mA IOL = spec'ed Drive High-level output current, slow slew rate2 IOH_S VOH =0.8*OVDD Std Drive High Drive Max Drive VOH =0.8*OVDD Std Drive High Drive Max Drive VOL =0.2*OVDD Std Drive High Drive Max Drive VOL =0.2*OVDD Std Drive High Drive Max Drive - - - - - - - VI = 0 VI = OVDD VI = 0 VI = OVDD VI = 0 VI = OVDD VI = OVDD or 0 Min OVDD -0.151 0.8*OVDD - - -2 -4 -8 - -4 -6 -8 - 2 4 8 - 4 6 8 0.7*OVDD 0 0.25 0.5*VDD - 70 61 - - - - - - - - - 100 100 0.33 - - - OVDD 0.3*VDD - - 0.5*VDD 268 343 250 100 25 0.1 0.25 28 2 nA A A A A A V V V V V K - mA - mA - mA Typ - - - - - Max - - 0.15 0.2*OVDD - mA Units V V VV High-level output current, fast slew rate2 IOH_F Low-level output current, slow slew rate2 IOL_S Low-level output current, fast slew rate2 IOL_F High-Level DC input voltage3 Low-Level DC input voltage Input Hysteresis Schmitt trigger VT+ Schmitt trigger VTPull-up resistor (100 K PU) Pull-down resistor (100 K PD) Input current (no PU/PD) 5 1, 4 3 VIH VIL VHYS VT + VT RPU RPD IIN IIN IIN IZ Input current (100 K PU) Input current (100 K PD) Tri-state Hi-Z input current 1 2 Power rail for output driver 1.75 - 3.1 V. Tested per I/O pad. 3 V , V ,V IH IL T+ and VT- for the pads in supply groups NVCC3-NVCC10 are referenced to OVDD. 4 Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled. 5 Typ condition: typ model, 1.875 V and 25C. Max condition: bcs model, 3.3 V and 105C. i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 67 Electrical Characteristics Table 15. DDR (Double Data Rate) I/O Pads DC Electrical Parameters Parameter High-level output voltage1 Symbol VOH Test Conditions IOH = -1 mA IOH = spec'ed Drive Low-level output voltage VOL IOL = 1 mA IOL = spec'ed Drive High-level output current2 IOH VOH =0.8*OVDD Std Drive High Drive Max Drive DDR Drive VOL=0.2*OVDD Std Drive High Drive Max Drive DDR Drive - - VI = 0 VI = OVDD VI = OVDD or 0 Min OVDD -0.12 0.8*OVDD - - -3.6 -7.2 -10.8 -14.4 - 3.6 7.2 10.8 14.4 0.7*OVDD -0.3 - - - OVDD OVDD+0.3 0 - - - 0.3*OVDD 900 140 2 V V nA nA A - mA Typ - - - - - Max - - 0.08 0.2*OVDD - Units V V V V mA Low-level output current2 IOL High-Level DC input voltage of CMOS receiver Low-Level DC input voltage of CMOS receiver Low-level input current3 High-level input current Tri-state Hi-Z current 1 2 VIH VIL IIL IIH IZ Max operating voltage for DDR pads with all drive strengths is 1.95 V. Tested per I/O pad. 3 Input current conditions: Typical condition: typ model, 1.875 V and 25C. Max condition: bcs model, 3.3 V and 105C 4.3.2 AC Electrical Characteristics Figure 3 depicts the load circuit for output pads. Figure 4 depicts the output pad transition time waveform. The range of operating conditions appears in Table 16 for slow general I/O, Table 17 for fast general I/O, and Table 18 for DDR I/O (unless otherwise noted). From Output Under Test Test Point CL CL includes package, probe and jig capacitance Figure 3. Load Circuit for Output Pad i.MX31/i.MX31L Advance Information, Rev. 1.4 68 Preliminary Freescale Semiconductor Electrical Characteristics OVDD 80% 20% PA1 PA1 80% 20% Output (at pad) 0V Figure 4. Output Pad Transition Time Waveform Table 16. AC Electrical Characteristics of Slow1 General I/O Pads ID PA1 Parameter Output Pad Transition Times (Max Drive) Output Pad Transition Times (High Drive) Output Pad Transition Times (Std Drive) 1 Symbol tpr tpr tpr Test Condition 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF Min 0.92 1.5 1.52 2.75 2.79 5.39 Typ 1.95 2.98 Max 3.17 4.75 4.81 8.42 8.56 16.43 Units ns ns ns Fast/slow characteristic is selected per GPIO I/O pad (where available) by "slew rate" control. See Table 6. Table 17. AC Electrical Characteristics of Fast1 General I/O Pads 2 ID PA1 Parameter Output Pad Transition Times (Max Drive) Output Pad Transition Times (High Drive) Output Pad Transition Times (Std Drive) 1 2 Symbol tpr tpr tpr Test Condition 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF Min 0.68 1.34 .91 1.79 1.36 2.68 Typ 1.33 2.6 1.77 3.47 2.64 5.19 Max 2.07 4.06 2.74 5.41 4.12 8.11 Units ns ns ns Fast/slow characteristic is selected per GPIO I/O pad (where available) by "slew rate" control. See Table 6. Recommended max operating voltage for GPIO in fast mode with all drive strengths is 1.95 V. Absolute maximum is described in Table 9. Table 18. AC Electrical Characteristics of DDR I/O Pads 1 ID PA1 Parameter Output Pad Transition Times (DDR Drive) Output Pad Transition Times (Max Drive) Output Pad Transition Times (High Drive) Output Pad Transition Times (Std Drive) 1 Symbol tpr tpr tpr tpr Test Condition 25 pF 50 pF 25 pF 50 pF 25 pF 35 pF 25 pF 50 pF Min 0.51 0.97 0.67 1.29 .99 1.93 1.96 3.82 Typ 0.82 1.58 1.08 2.1 1.61 3.13 3.19 6.24 Max 1.28 2.46 1.69 3.27 2.51 4.89 4.99 9.73 Units ns ns ns ns Absolute max operating voltage for DDR pads with all drive strengths is 1.95 V. i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 69 Electrical Characteristics 4.3.3 Clock Amplifier Module (CAMP) Electrical Characteristics This section outlines the Clock Amplifier Module (CAMP) specific electrical characteristics. Table 19 shows clock amplifier electrical characteristics. Table 19. Clock Amplifier Electrical Characteristics Parameter Input Frequency VIL (for square input) VIH (for square input) Sinusoidal Input Amplitude Duty Cycle 1 2 Min 8.0 0 (VDD 1- 0.25) 0.4 45 2 Typ - - - - 50 Max 34.0 0.3 3 VDD 55 Units MHz V V Vp-p % VDD is the supply voltage of CAMP This value of the sinusoidal input will be measured through characterization. 4.3.4 1-Wire Electrical Specifications Figure 5 depicts the RPP timing, and Table 20 lists the RPP timing parameters. OWIRE Tx "Reset Pulse" 1-Wire bus (BATT_LINE) DS2502 Tx "Presence Pulse" OW2 OW1 OW3 OW4 Figure 5. Reset and Presence Pulses (RPP) Timing Diagram Table 20. RPP Sequence Delay Comparisons Timing Parameters ID OW1 OW2 OW3 OW4 Parameters Reset Time Low Presence Detect High Presence Detect Low Reset Time High Symbol tRSTL tPDH tPDL tRSTH Min 480 15 60 480 Typ 511 - - 512 Max - 60 240 - Units s s s s Figure 6 depicts Write 0 Sequence timing, and Table 21 lists the timing parameters. i.MX31/i.MX31L Advance Information, Rev. 1.4 70 Preliminary Freescale Semiconductor Electrical Characteristics OW6 1-Wire bus (BATT_LINE) OW5 Figure 6. Write 0 Sequence Timing Diagram Table 21. WR0 Sequence Timing Parameters ID OW5 OW6 Parameter Write 0 Low Time Transmission Time Slot Symbol tWR0_low tSLOT Min 60 OW5 Typ 100 117 Max 120 120 Units s s Figure 7 depicts Write 1 Sequence timing, Figure 8 depicts the Read Sequence timing, and Table 22 lists the timing parameters. OW8 1-Wire bus (BATT_LINE) OW7 Figure 7. Write 1 Sequence Timing Diagram OW8 1-Wire bus (BATT_LINE) OW7 OW9 Figure 8. Read Sequence Timing Diagram Table 22. WR1 /RD Timing Parameters ID OW7 OW8 OW9 Parameter Write 1 / Read Low Time Transmission Time Slot Release Time Symbol tLOW1 tSLOT tRELEASE Min 1 60 15 Typ 5 117 - Max 15 120 45 Units s s s i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 71 Electrical Characteristics 4.3.5 ATA Electrical Specifications (ATA Bus, Bus Buffers) This section discusses ATA electricals and explains how to make sure the ATA interface meets timing. To meet electrical spec on the ATA bus, several requirements must be met. For a detailed description, refer to the ATA specification. This electrical spec must be met for the pads used on the ATA I/Os if no bus buffers and bus transceivers are used. Alternative is to use bus buffers. This is the only way to operate the ATA interface if 3.3 Volt or 5.0 Volt compatibility on the ATA bus is wanted, and no 3.3 Volt or 5.0 Volt tolerant pads on the device are available. The use of bus buffers introduces delay on the bus and introduces skew between signal lines. These factors make it difficult to operate the bus at the highest speed (UDMA-5) when bus buffers are used. If fast UDMA mode operation is needed, this may not be compatible with bus buffers. Another area of attention is the slew rate limit imposed by the ATA specification on the ATA bus. According to this limit, any signal driven on the bus should have a slew rate between 0.4 and 1.2 V/ns with a 40 pF load. Not many vendors of bus buffers specify slew rate of the outgoing signals. When bus buffers are used, the ata_data bus buffer is special. This is a bidirectional bus buffer, so a direction control signal is needed. This direction control signal is ata_buffer_en. When its high, the bus should drive from host to device. When its low, the bus should drive from device to host. Steering of the signal is such that contention on the host and device tri-state busses is always avoided. 4.3.5.1 Timing Parameters In the timing equations, some timing parameters are used. These parameters depend on the implementation of the ATA interface on silicon, the bus buffer used, the cable delay and cable skew. Table 23 shows ATA timing parameters. Table 23. ATA Timing Parameters Name T ti_ds ti_dh tco Bus clock period (ipg_clk_ata) Set-up time ata_data to ata_iordy edge (UDMA-in only) hold time ata_iordy edge to ata_data (UDMA-in only) propagation delay bus clock L-to-H to ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data, ata_buffer_en set-up time ata_data to bus clock L-to-H set-up time ata_iordy to bus clock H-to-L hold time ata_iordy to bus clock H to L Description Value/ Contributing Factor1 peripheral clock frequency 11 ns 6 ns 15 ns tsu tsui thi 19 ns 9 ns 5 ns i.MX31/i.MX31L Advance Information, Rev. 1.4 72 Preliminary Freescale Semiconductor Electrical Characteristics Table 23. ATA Timing Parameters (continued) Name tskew1 Description Max difference in propagation delay bus clock L-to-H to any of following signals ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data (write), ata_buffer_en Max difference in buffer propagation delay for any of following signals ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data (write), ata_buffer_en Max difference in buffer propagation delay for any of following signals ata_iordy, ata_data (read) Max buffer propagation delay cable propagation delay for ata_data cable propagation delay for control signals ata_dior, ata_diow, ata_iordy, ata_dmack Max difference in cable propagation delay between ata_iordy and ata_data (read) Max difference in cable propagation delay between (ata_dior, ata_diow, ata_dmack) and ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_data(write) Max difference in cable propagation delay without accounting for ground bounce Value/ Contributing Factor1 7 ns tskew2 transceiver tskew3 tbuf tcable1 tcable2 tskew4 tskew5 tskew6 1 transceiver transceiver cable cable cable cable cable Values provided where applicable. 4.3.5.2 PIO Mode Timing Figure 9 shows timing for PIO read, and Table 24 lists the timing parameters for PIO read. Figure 9. PIO Read Timing Diagram Table 24. PIO Read Timing Parameters ATA Parameter Parameter from Figure 9 t1 t2 t9 t1 t2r t9 Value t1 (min) = time_1 * T - (tskew1 + tskew2 + tskew5) t2 min) = time_2r * T - (tskew1 + tskew2 + tskew5) t9 (min) = time_9 * T - (tskew1 + tskew2 + tskew6) Controlling Variable time_1 time_2r time_3 i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 73 Electrical Characteristics Table 24. PIO Read Timing Parameters (continued) ATA Parameter Parameter from Figure 9 t5 t6 tA trd t5 t6 tA trd1 Value t5 (min) = tco + tsu + tbuf + tbuf + tcable1 + tcable2 0 tA (min) = (1.5 + time_ax) * T - (tco + tsui + tcable2 + tcable2 + 2*tbuf) trd1 (max) = (-trd) + (tskew3 + tskew4) trd1 (min) = (time_pio_rdx - 0.5)*T - (tsu + thi) (time_pio_rdx - 0.5) * T > tsu + thi + tskew3 + tskew4 t0 (min) = (time_1 + time_2 + time_9) * T Controlling Variable If not met, increase time_2. - time_ax time_pio_rdx t0 - time_1, time_2r, time_9 Figure 10 shows timing for PIO write, and Table 25 lists the timing parameters for PIO write. Figure 10. Multiword DMA (MDMA) Timing Table 25. PIO Write Timing Parameters ATA Parameter Parameter from Figure 10 t1 t2 t9 t3 t4 tA t0 t1 t2w t9 - t4 tA - Value t1 (min) = time_1 * T - (tskew1 + tskew2 + tskew5) t2 (min) = time_2w * T - (tskew1 + tskew2 + tskew5) t9 (min) = time_9 * T - (tskew1 + tskew2 + tskew6) t3 (min) = (time_2w - time_on)* T - (tskew1 + tskew2 +tskew5) t4 (min) = time_4 * T - tskew1 tA = (1.5 + time_ax) * T - (tco + tsui + tcable2 + tcable2 + 2*tbuf) t0(min) = (time_1 + time_2 + time_9) * T Controlling Variable time_1 time_2w time_9 If not met, increase time_2w. time_4 time_ax time_1, time_2r, time_9 i.MX31/i.MX31L Advance Information, Rev. 1.4 74 Preliminary Freescale Semiconductor Electrical Characteristics Table 25. PIO Write Timing Parameters (continued) ATA Parameter Parameter from Figure 10 - - - - Value Avoid bus contention when switching buffer on by making ton long enough. Avoid bus contention when switching buffer off by making toff long enough. Controlling Variable - - Figure 11 shows timing for MDMA read, Figure 12 shows timing for MDMA write, and Table 26 lists the timing parameters for MDMA read and write. Figure 11. MDMA Read Timing Diagram Figure 12. MDMA Write Timing Diagram Table 26. MDMA Read and Write Timing Parameters Parameter from Figure 11, Figure 12 tm td, td1 tk Controlling Variable ATA Parameter Value tm, ti td tk tm (min) = ti (min) = time_m * T - (tskew1 + tskew2 + tskew5) td1.(min) = td (min) = time_d * T - (tskew1 + tskew2 + tskew6) tk.(min) = time_k * T - (tskew1 + tskew2 + tskew6) time_m time_d time_k i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 75 Electrical Characteristics Table 26. MDMA Read and Write Timing Parameters (continued) Parameter from Figure 11, Figure 12 - tgr tfr - - - tkjn ton toff t0 (min) = (time_d + time_k) * T tgr (min-read) = tco + tsu + tbuf + tbuf + tcable1 + tcable2 tgr.(min-drive) = td - te(drive) tfr (min-drive) = 0 tg (min-write) = time_d * T - (tskew1 + tskew2 + tskew5) tf (min-write) = time_k * T - (tskew1 + tskew2 + tskew6) tL (max) = (time_d + time_k-2)*T - (tsu + tco + 2*tbuf + 2*tcable2) tn= tj= tkjn = (max(time_k,. time_jn) * T - (tskew1 + tskew2 + tskew6) ton = time_on * T - tskew1 toff = time_off * T - tskew1 Controlling Variable ATA Parameter Value t0 tg(read) tf(read) tg(write) tf(write) tL tn, tj - time_d, time_k time_d - time_d time_k time_d, time_k time_jn - 4.3.5.3 UDMA In Timing Figure 13 shows timing when the UDMA in transfer starts, Figure 14 shows timing when the UDMA in host terminates transfer, Figure 15 shows timing when the UDMA in device terminates transfer, and Table 27 lists the timing parameters for UDMA in burst. Figure 13. UDMA In Transfer Starts Timing Diagram i.MX31/i.MX31L Advance Information, Rev. 1.4 76 Preliminary Freescale Semiconductor Electrical Characteristics Figure 14. UDMA In Host Terminates Transfer Timing Diagram Figure 15. UDMA In Device Terminates Transfer Timing Diagram Table 27. UDMA In Burst Timing Parameters Parameter from Figure 13, Figure 14, Figure 15 tack tenv tds1 tdh1 ATA Parameter Description Controlling Variable tack tenv tds tdh tack (min) = (time_ack * T) - (tskew1 + tskew2) tenv (min) = (time_env * T) - (tskew1 + tskew2) tenv (max) = (time_env * T) + (tskew1 + tskew2) tds - (tskew3) - ti_ds > 0 tdh - (tskew3) -ti_dh > 0 time_ack time_env tskew3, ti_ds, ti_dh should be low enough i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 77 Electrical Characteristics Table 27. UDMA In Burst Timing Parameters (continued) Parameter from Figure 13, Figure 14, Figure 15 tc1 trp tx11 tmli1 tzah tdzfs tcvh ton toff (tcyc - tskew) > T trp (min) = time_rp * T - (tskew1 + tskew2 + tskew6) (time_rp * T) - (tco + tsu + 3T + 2 *tbuf + 2*tcable2) > trfs (drive) tmli1 (min) = (time_mlix + 0.4) * T tzah (min) = (time_zah + 0.4) * T tdzfs = (time_dzfs * T) - (tskew1 + tskew2) tcvh = (time_cvh *T) - (tskew1 + tskew2) ton = time_on * T - tskew1 toff = time_off * T - tskew1 ATA Parameter Description Controlling Variable tcyc trp - tmli tzah tdzfs tcvh - 1 T big enough time_rp time_rp time_mlix time_zah time_dzfs time_cvh - There is a special timing requirement in the ATA host that requires the internal DIOW to go only high 3 clocks after the last active edge on the DSTROBE signal. The equation given on this line tries to capture this constraint. 2. Make ton and toff big enough to avoid bus contention 4.3.5.4 UDMA Out Timing Figure 16 shows timing when the UDMA out transfer starts, Figure 17 shows timing when the UDMA out host terminates transfer, Figure 18 shows timing when the UDMA out device terminates transfer, and Table 28 lists the timing parameters for UDMA out burst. Figure 16. UDMA Out Transfer Starts Timing Diagram i.MX31/i.MX31L Advance Information, Rev. 1.4 78 Preliminary Freescale Semiconductor Electrical Characteristics Figure 17. UDMA Out Host Terminates Transfer Timing Diagram Figure 18. UDMA Out Device Terminates Transfer Timing Diagram Table 28. UDMA Out Burst Timing Parameters Parameter from Figure 16, Figure 17, Figure 18 tack tenv tdvs tdvh tcyc - ATA Parameter Value Controlling Variable tack tenv tdvs tdvh tcyc t2cyc tack (min) = (time_ack * T) - (tskew1 + tskew2) tenv (min) = (time_env * T) - (tskew1 + tskew2) tenv (max) = (time_env * T) + (tskew1 + tskew2) tdvs = (time_dvs * T) - (tskew1 + tskew2) tdvs = (time_dvh * T) - (tskew1 + tskew2) tcyc = time_cyc * T - (tskew1 + tskew2) t2cyc = time_cyc * 2 * T time_ack time_env time_dvs time_dvh time_cyc time_cyc i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 79 Electrical Characteristics Table 28. UDMA Out Burst Timing Parameters (continued) Parameter from Figure 16, Figure 17, Figure 18 trfs tdzfs tss tdzfs_mli tli1 tli2 tli3 tcvh ton toff ATA Parameter Value Controlling Variable trfs1 - tss tmli tli tli tli tcvh - trfs = 1.6 * T + tsui + tco + tbuf + tbuf tdzfs = time_dzfs * T - (tskew1) tss = time_ss * T - (tskew1 + tskew2) tdzfs_mli =max (time_dzfs, time_mli) * T - (tskew1 + tskew2) tli1 > 0 tli2 > 0 tli3 > 0 tcvh = (time_cvh *T) - (tskew1 + tskew2) ton = time_on * T - tskew1 toff = time_off * T - tskew1 - time_dzfs time_ss - - - - time_cvh - 4.3.6 AUDMUX Electrical Specifications The AUDMUX provides a programmable interconnect logic for voice, audio and data routing between internal serial interfaces (SSI) and external serial interfaces (audio and voice codecs). The AC timing of AUDMUX external pins is hence governed by the SSI module. Please refer to their respective electrical specifications. 4.3.7 CSPI Electrical Specifications This section describes the electrical information of the CSPI. 4.3.7.1 CSPI Timing Figure 19 and Figure 20 depict the master mode and slave mode timings of CSPI, and Table 29 lists the timing parameters. i.MX31/i.MX31L Advance Information, Rev. 1.4 80 Preliminary Freescale Semiconductor Electrical Characteristics CSPIx_DRYN CS11 CSPIx_CS_x CS1 CS3 CS2 CS6 CS4 CS5 CSPIx_CLK CS7 CSPIx_DO CS9 CSPIx_DI CS10 CS8 CS3 CS2 Figure 19. CSPI Master Mode Timing Diagram NOTE CSPI1_DRYN is connected to CSPI1_CS_1, CSPI2_DRYN is connected to DAM2_T_CLK CSPIx_CS_x CS1 CSPIx_CLK CS9 CSPIx_DI CS7 CSPIx_DO CS8 CS10 CS3 CS2 CS3 CS2 CS6 CS4 CS5 Figure 20. CSPI Slave Mode Timing Diagram Table 29. CSPI Interface Timing Parameters ID CS1 CS2 CS3 CS4 CS5 CS6 CS7 CS8 Parameter CSPIx_CLK Cycle Time CSPIx_CLK High or Low Time CSPIx_CLK Rise or Fall CSPIx_CS_x pulse width CSPIx_CS_x Lead Time (CS setup time) CSPIx_CS_x Lag Time (CS hold time) CSPIx_DO Setup Time CSPIx_DO Hold Time Symbol tclk tSW tRISE/FALL tCSLH tSCS tHCS tSmosi tHmosi i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 81 Min 60 30 - 25 25 25 5 5 Max - - 7.6 - - - - - Units ns ns ns ns ns ns ns ns Electrical Characteristics Table 29. CSPI Interface Timing Parameters (continued) ID CS9 CS10 CS11 CSPIx_DI Setup Time CSPIx_DI Hold Time CSPIx_DRYN Setup Time Parameter Symbol tSmiso tHmiso tSDRY Min 5 5 5 Max - - - Units ns ns ns 4.3.8 DPLL Electrical Specifications The three PLL's of the MX31/MX31L (MCU, USB, and Serial PLL) are all based on same DPLL design. The characteristics provided herein apply to all of them, except where noted explicitly. The PLL characteristics are provided based on measurements done for both sources--external clock source (CKIH), and FPM (Frequency Pre-Multiplier) source. 4.3.8.1 Electrical Specifications Table 30. DPLL Specifications Parameter Min 10 Typ 32; 32.768, 38.4 1 10 10 - - 1.4 - - - - - - - - - - - - - - - - - - Max 100 - 16 35 MHz s s s V mA mV mV mV ns ns Unit MHz MHz Comments - - - - - Cycles of divided reference clock. In addition to the frequency - - Fmodulation < 50 kHz Fmodulation < 300 kHz Fmodulation < 300 kHz Measured on CKO pin Measured on CKO pin Table 30 lists the DPLL specification. CKIH reference frequency CKIL referencer frequency (FPM enable mode) Predivision factor PLL reference frequency range after Predivider Maximum allowed reference clock phase noise. Frequency lock time (FOL mode or non-integer MF) Phase lock time PLL Power supply voltage Single PLL current consumption Maximum allowed PLL supply voltage ripple Maximum allowed PLL supply voltage ripple Maximum allowed PLL supply voltage ripple PLL output clock phase jitter PLL output clock phase jitter 100 398 100 1.6 4.4 25 20 25 5.2 420 i.MX31/i.MX31L Advance Information, Rev. 1.4 82 Preliminary Freescale Semiconductor Electrical Characteristics 4.3.9 EMI Electrical Specifications This section provides electrical parametrics and timings for EMI module. 4.3.9.1 NAND Flash Controller Interface (NFC) There are two modes of operations for the NFC--default and ONE_CYCLE. Normal NFC mode--using two flash clock cycles for one access of RE and WE. AC parameters calculation for this mode assume the flash clock cycle frequency is 22.5 MHz (as an example). One-Cycle NFC mode--using one flash cycle for one access of RE and WE. AC parameters calculation for this mode assume the flash clock cycle frequency that is 33.5 MHz (as an example). 4.3.9.1.1 Normal NFC Mode (Default) The flash clock maximum frequency goes up to 50 MHz. Figure 21, Figure 22, Figure 23, and Figure 24 depict the relative timing requirements among different signals of the NFC at module level, for normal mode, and Table 31 lists the timing parameters. NFCLE NF1 NF3 NFCE NF5 NFWE NF6 NFALE NF8 NF9 NFIO[7:0] Command NF7 NF2 NF4 Figure 21. Command Latch Cycle Timing DIagram i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 83 Electrical Characteristics NFCLE NF1 NF3 NFCE NF10 NF11 NF5 NFWE NF6 NFALE NF8 NF9 NFIO[7:0] Address NF7 NF4 Figure 22. Address Latch Cycle Timing DIagram NFCLE NF1 NF3 NFCE NF10 NF11 NF5 NFWE NF6 NFALE NF8 NF9 NFIO[15:0] Data to NF NF7 Figure 23. Write Data Latch Cycle Timing DIagram i.MX31/i.MX31L Advance Information, Rev. 1.4 84 Preliminary Freescale Semiconductor Electrical Characteristics NFCLE NFCE NF14 NF15 NF13 NFRE NF16 NFRB NF12 NFIO[15:0] Data from NF NF17 Figure 24. Read Data Latch Cycle Timing DIagram Table 31. NFC Target Timing Parameters Relationship to NFC clock Period (T) Min NF1 NF2 NF3 NF4 NF5 NF6 NF7 NF8 NF9 NFCLE Setup Time NFCLE Hold Time NFCE Setup Time NFCE Hold Time NF_WP Pulse Width NFALE Setup Time NFALE Hold Time Data Setup Time Data Hold Time tCLS tCLH tCS tCH tWP tALS tALH tDS tDH tWC tWH tRR tRP tRC tREH tDSR tDHR T T T T T T T T T 2T T 6T 1.5T 2T 0.5T - - Max - - - - - - - - - - - - - - - - - Min 45 45 90 45 45 45 45 90 45 90 45 270 67.5 90 22.5 15 5 Max - - - - - - - - - - - - - - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ID Parameter Symbol Unit NF10 Write Cycle Time NF11 NFWE Hold Time NF12 Ready to NFRE Low NF13 NFRE Pulse Width NF14 READ Cycle Time NF15 NFRE High Hold Time NF16 Data Setup on READ NF17 Data Hold on READ NOTE High is defined as 80% of signal value and low is defined as 20% of signal value. i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 85 Electrical Characteristics NOTE Timing for HCLK is 133 MHz and internal LCLK (flash clock) is 22.5 MHz (45 ns). All timings are listed according to this LCLK frequency (multiples of LCLK phases) except NF16, which is not LCLK related. 4.3.9.1.2 One-Cycle NFC Mode Figure 25, Figure 26, Figure 27, and Figure 28 depict the relative timing requirements among different signals of the NFC at module level for one-cycle mode, and Table 32 lists the timing parameters. NFCLE NF1_one NF3_one NFCE NF2_one NF4_one NF5_one NFWE NF6_one NFALE NF8_one NF9_one NFIO[7:0] command NF7_one Figure 25. Command Latch Cycle Timing DIagram--One Flash Clock Cycle NFCLE NF1_one NF3_one NFCE NF10_one NF11_one NF5_one NFWE NF6_one NFALE NF8_one NF9_one NFIO[7:0] Address NF7_one NF4_one Figure 26. Address Latch Cycle Timing DIagram--One Flash Clock Cycle i.MX31/i.MX31L Advance Information, Rev. 1.4 86 Preliminary Freescale Semiconductor Electrical Characteristics NFCLE NF1_one NF3_one NFCE NF10_one NF11_one NF5_one NFWE NF6_one NFALE NF8_one NF9_one NFIO[15:0] Data to NF NF7_one Figure 27. Write Data Latch Cycle Timing DIagram--One Flash Clock Cycle NFCLE NFCE NF14_one NF15_one NF13_one NFRE NF16_one NFRB NF12_one NFIO[15:0] Data from NF NF17_one Figure 28. Read Data Latch Cycle Timing DIagram--One Flash Clock Cycle Table 32. NFC Target Timing Parameters--One Flash Clock Cycle ID NF1_one NF2_one NF3_one NF4_one NF5_one Parameter NFCLE Setup Time NFCLE Hold Time NFCE Setup Time NFCE Hold Time NF_WP Pulse Width Symbol tCLS tCLH tCS tCH tWP Min 30 30 60 45 15 Max - - - - - Unit ns ns ns ns ns i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 87 Electrical Characteristics Table 32. NFC Target Timing Parameters--One Flash Clock Cycle (continued) ID NF6_one NF7_one NF8_one NF9_one NF10_one NF11_one NF12_one NF13_one NF14_one NF15_one NF16_one NF17_one Parameter NFALE Setup Time NFALE Hold Time Data Setup Time Data Hold Time Write Cycle Time NFWE Hold Time Ready to NFRE Low NFRE Pulse Width READ Cycle Time NFRE High Hold Time Data Setup on READ Data Hold on READ Symbol tALS tALH tDS tDH tWC tWH tRR tRP tRC tREH tDSR tDHR Min 30 30 15 15 30 15 180 15 30 15 12 5 Max - - - - - - - - - - - - Unit ns ns ns ns ns ns ns ns ns ns ns ns NOTE High is defined as 80% of signal value and low is defined as 20% of signal value. NOTE Timing for HCLK is 133 MHz and internal LCLK (flash clock) is 33.25 MHz (30 ns). All timings are listed according to this LCLK frequency. 4.3.9.2 Wireless External Interface Module (WEIM) All WEIM output control signals may be asserted and deasserted by internal clock related to BCLK rising edge or falling edge according to corresponding assertion/negation control fields. Address always begins related to BCLK falling edge but may be ended both on rising and falling edge in muxed mode according to control register configuration. Output data begins related to BCLK rising edge except in muxed mode where both rising and falling edge may be used according to control register configuration. Input data, ECB and DTACK all captured according to BCLK rising edge time. Figure 29 depicts the timing of the WEIM module, and Table 33 lists the timing parameters. NOTE ECB and DTACK signals mentioned in this section can be connected to one input pad--ECB, although the WEIM design has those two signals as individual inputs. In this case, this PAD will be connected to the 2 WEIM inputs. i.MX31/i.MX31L Advance Information, Rev. 1.4 88 Preliminary Freescale Semiconductor Electrical Characteristics , WEIM Outputs Timing WE22 WE21 BCLK (for rising edge timing) ... ... BCLK (for falling edge timing) Address CS[x] RW WE3 WE5 WE4 WE6 WE1 WE2 WE23 OE WE7 WE8 EB[x] WE9 WE10 WE11 LBA WE13 Output Data WE12 WE14 WEIM Inputs timing BCLK (for rising edge timing) WE16 Input Data WE15 WE18 ECB WE17 WE20 DTACK WE19 Figure 29. WEIM Bus Timing Diagram Table 33. WEIM Bus Timing Parameters 1.8 V ID Parameter Min WE1 WE2 WE3 Clock fall to address valid Clock rise/fall to address invalid Clock rise/fall to CS[x] valid -2 -2 -3 Max 7 7 3 ns ns ns Unit i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 89 Electrical Characteristics Table 33. WEIM Bus Timing Parameters (continued) 1.8 V ID Parameter Min WE4 WE5 WE6 WE7 WE8 WE9 WE10 WE11 WE12 WE13 WE14 WE15 WE16 WE15 WE16 WE17 WE18 WE17 WE18 WE19 WE20 WE20 WE21 WE22 WE23 1 2 Unit Max 3 3 3 3 3 3 3 3 3 10 10 10 0 10 0 10 0 10 0 - 4 12 Tcycle/ 2-3 Tcycle/ 2-3 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Clock rise/fall to CS[x] invalid Clock rise/fall to RW Valid Clock rise/fall to RW Invalid Clock rise/fall to OE Valid Clock rise/fall to OE Invalid Clock rise/fall to EB[x] Valid Clock rise/fall to EB[x] Invalid Clock rise/fall to LBA Valid Clock rise/fall to LBA Invalid Clock rise/fall to Output Data Valid Clock rise to Output Data Invalid Input Data Valid to Clock rise, FCE=0 Cloc/k rise to Input Data Invalid, FCE=0 Input Data Valid to Clock rise, FCE=1 Clock rise to Input Data Invalid, FCE=1 ECB setup time, FCE=0 ECB hold time, FCE=0 ECB setup time, FCE=1 ECB hold time, FCE=1 DTACK setup time DTACK hold time DTACK hold time (Level sensitive mode, EW=1 implies wsc < 111111) BCLK High Level Width2, 3 BCLK Low Level Width2, 3 BCLK Cycle time2 1 -3 -3 -3 -3 -3 -3 -3 -3 -3 -3.5 -3.5 -2 -7 -2 -7 -2 -7 -2 -7 - 0 6 - - - Not required. BCLK parameters are being measured from the 50% VDD. 3 The actual cycle time is derived from the AHB bus clock frequency. NOTE High is defined as 80% of signal value and low is defined as 20% of signal value. i.MX31/i.MX31L Advance Information, Rev. 1.4 90 Preliminary Freescale Semiconductor Electrical Characteristics NOTE Test conditions: pad voltage, 1.75 V-1.95 V; pad capacitance, 25 pF. Recommended drive strength for all controls, address, and BCLK is Max drive. Figure 30, Figure 31, Figure 32, Figure 33, Figure 34, and Figure 35 depict some examples of basic WEIM accesses to external memory devices with the timing parameters mentioned in Table 33 for specific control parameter settings. BCLK WE1 ADDR CS[x] RW WE11 LBA WE7 WE12 Last Valid Address WE3 V1 WE2 Next Address WE4 OE WE8 EB[y] WE9 WE10 WE16 DATA V1 WE15 Figure 30. Asynchronous Memory Timing Diagram for Read Access--WSC=1 BCLK WE1 ADDR CS[x] Last Valid Address WE3 WE5 RW LBA OE WE9 WE10 WE14 DATA WE13 V1 WE11 WE12 V1 WE4 WE6 WE2 Next Address EB[y] Figure 31. Asynchronous Memory Timing Diagram for Write Access-- WSC=1, EBWA=1, EBWN=1, LBN=1 i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 91 Electrical Characteristics BCLK WE1 ADDR Last Valid Addr CS[x] RW WE11 WE12 WE8 WE3 Address V1 WE2 Address V2 WE4 LBA OE EB[y] WE7 WE9 WE18 WE18 WE10 ECB WE17 WE16 DATA WE15 V1 V1+2 Halfword Halfword WE17 WE16 V2 Halfword V2+2 Halfword WE15 Figure 32. Synchronous Memory Timing Diagram for Two Non-Sequential Read Accesses-- WSC=2, SYNC=1, DOL=0 BCLK WE1 ADDR Last Valid Addr CS[x] WE3 Address V1 WE2 WE4 RW WE5 WE11 WE12 WE6 LBA OE EB[y] WE9 WE10 WE18 ECB WE17 WE14 DATA WE13 V1 WE13 WE14 V1+4 V1+8 V1+12 Figure 33. Synchronous Memory TIming Diagram for Burst Write Access-- BCS=1, WSC=4, SYNC=1, DOL=0, PSR=1 i.MX31/i.MX31L Advance Information, Rev. 1.4 92 Preliminary Freescale Semiconductor Electrical Characteristics WE1 ADDR/ Last Valid Addr M_DATA CS[x] WE3 BCLK WE2 Address V1 WE13 Write Data WE14 WE4 RW WE5 Write WE11 WE12 WE6 LBA OE EB[y] WE9 WE10 Figure 34. Muxed A/D Mode Timing Diagram for Asynchronous Write Access-- WSC=7, LBA=1, LBN=1, LAH=1 BCLK WE1 ADDR/ Last Valid Addr M_DATA WE3 CS[x] WE2 Address V1 WE16 Read Data WE15 WE4 RW WE11 LBA WE12 OE EB[y] WE9 WE7 WE8 WE10 Figure 35. Muxed A/D Mode Timing Diagram for Asynchronous Read Access-- WSC=7, LBA=1, LBN=1, LAH=1, OEA=7 4.3.9.3 SDRAM (DDR and SDR) Memory Controller Figure 36, Figure 37, Figure 38, Figure 39, Figure 40, and Figure 41 depict the timings pertaining to the SDRAMC module, which interfaces Mobile DDR or SDR SDRAM. Table 34, Table 35, Table 36, Table 37, Table 38, and Table 39 list the timing parameters. i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 93 Electrical Characteristics SD1 SDCLK SDCLK SD4 CS SD5 SD4 RAS SD5 SD4 CAS SD4 SD5 WE SD6 ADDR ROW/BA SD5 SD2 SD3 SD7 COL/BA SD10 SD8 SD9 Data DQ SD4 DQM SD5 Note: CKE is high during the read/write cycle. Figure 36. SDRAM Read Cycle Timing Diagram Table 34. DDR/SDR SDRAM Read Cycle Timing Parameters ID SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 Parameter SDRAM clock high-level width SDRAM clock low-level width SDRAM clock cycle time CS, RAS, CAS, WE, DQM, CKE setup time CS, RAS, CAS, WE, DQM, CKE hold time Address output delay time Address output hold time SDRAM access time Symbol tCH tCL tCK tCMS tCMH tAS tAH tAC Min 3.4 3.4 7.5 2.0 1.8 2.0 1.8 - Max 4.1 4.1 - - - - - 6.47 Unit ns ns ns ns ns ns ns ns i.MX31/i.MX31L Advance Information, Rev. 1.4 94 Preliminary Freescale Semiconductor Electrical Characteristics Table 34. DDR/SDR SDRAM Read Cycle Timing Parameters (continued) ID SD9 SD10 1 Parameter Data out hold time1 Active to read/write command period Symbol tOH tRC Min 1.5 10 Max - - Unit ns clock Timing parameters are relevant only to SDR SDRAM. For the specific DDR SDRAM data related timing parameters, see Table 38 and Table 39. NOTE SDR SDRAM CLK parameters are being measured from the 50% point-that is, high is defined as 50% of signal value and low is defined as 50% of signal value. SD1 + SD2 does not exceed 7.5 ns for 133 MHz. NOTE The timing parameters similar to the ones used in the regular SDRAM data sheet. All output signals are driven by the ESDCTL at the negative edge of SDCLK and the parameters are measured at maximum memory frequency. i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 95 Electrical Characteristics SD1 SDCLK SDCLK SD2 SD3 SD4 CS SD5 RAS SD11 CAS SD5 SD4 SD4 SD4 WE SD5 SD7 SD6 ADDR BA ROW / BA SD13 DQ DATA COL/BA SD12 SD5 SD14 DQM Figure 37. SDR SDRAM Write Cycle Timing Diagram Table 35. SDR SDRAM Write Timing Parameters ID SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD11 SD12 Parameter SDRAM clock high-level width SDRAM clock low-level width SDRAM clock cycle time CS, RAS, CAS, WE, DQM, CKE setup time CS, RAS, CAS, WE, DQM, CKE hold time Address setup time Address hold time Precharge cycle period1 Symbol tCH tCL tCK tCMS tCMH tAS tAH tRP tRCD Min 3.4 3.4 7.5 2.0 1.8 2.0 1.8 1 1 Max 4.1 4.1 - - - - - 4 8 Unit ns ns ns ns ns ns ns clock clock Active to read/write command delay1 i.MX31/i.MX31L Advance Information, Rev. 1.4 96 Preliminary Freescale Semiconductor Electrical Characteristics Table 35. SDR SDRAM Write Timing Parameters (continued) ID SD13 SD14 1 Parameter Data setup time Data hold time Symbol tDS tDH Min 2.0 1.3 Max - - Unit ns ns SD11 and SD12 are determined by SDRAM controller register settings. NOTE SDR SDRAM CLK parameters are being measured from the 50% point--that is, high is defined as 50% of signal value and low is defined as 50% of signal value. SD1 SDCLK SDCLK SD2 SD3 CS RAS SD11 CAS SD10 SD10 WE ADDR SD6 BA ROW/BA SD7 DQ DQM Figure 38. SDRAM Refresh Timing Diagram Table 36. SDRAM Refresh Timing Parameters ID SD1 SD2 Parameter SDRAM clock high-level width SDRAM clock low-level width Symbol tCH tCL Min 3.4 3.4 Max 4.1 4.1 Unit ns ns i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 97 Electrical Characteristics Table 36. SDRAM Refresh Timing Parameters (continued) ID SD3 SD6 SD7 SD10 SD11 1 Parameter SDRAM clock cycle time Address setup time Address hold time Precharge cycle period1 Auto precharge command period1 Symbol tCK tAS tAH tRP tRC Min 7.5 1.8 1.8 1 2 Max - - - 4 20 Unit ns ns ns clock clock SD10 and SD11 are determined by SDRAM controller register settings. NOTE SDR SDRAM CLK parameters are being measured from the 50% point--that is, high is defined as 50% of signal value and low is defined as 50% of signal value. SDCLK CS RAS CAS WE ADDR BA CKE SD16 SD16 Don't care Figure 39. SDRAM Self-Refresh Cycle Timing Diagram NOTE The clock will continue to run unless both CKEs are low. Then the clock will be stopped in low state. i.MX31/i.MX31L Advance Information, Rev. 1.4 98 Preliminary Freescale Semiconductor Electrical Characteristics Table 37. SDRAM Self-Refresh Cycle Timing Parameters ID SD16 Parameter CKE output delay time Symbol tCKS Min 1.8 Max - Unit ns SDCLK SDCLK SD19 DQS (output) SD17 DQ (output) Data Data SD20 SD18 SD17 Data Data SD18 Data Data Data Data DQM (output) SD17 DM DM DM SD17 DM DM SD18 DM DM DM SD18 Figure 40. Mobile DDR SDRAM Write Cycle Timing Diagram Table 38. Mobile DDR SDRAM Write Cycle Timing Parameters ID SD17 SD18 SD19 SD20 Parameter DQ & DQM setup time to DQS DQ & DQM hold time to DQS Write cycle DQS falling edge to SDCLK output delay time. Write cycle DQS falling edge to SDCLK output hold time. Symbol tDS tDH tDSS tDSH Min 1.2 1.2 1.8 1.8 Max - - - - Unit ns ns ns ns NOTE SDRAM CLK and DQS related parameters are being measured from the 50% point--that is, high is defined as 50% of signal value and low is defined as 50% of signal value. i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 99 Electrical Characteristics SDCLK SDCLK SD23 DQS (input) SD22 SD21 DQ (input) Data Data Data Data Data Data Data Data Figure 41. Mobile DDR SDRAM DQ versus DQS and SDCLK Read Cycle Timing Diagram Table 39. Mobile DDR SDRAM Read Cycle Timing Parameters ID SD21 SD22 SD23 Parameter DQS - DQ Skew (defines the Data valid window in read cycles related to DQS). DQS DQ HOLD time from DQS DQS output access time from SDCLK posedge Symbol tDQSQ tQH tDQSCK Min - 2.3 - Max .85 - 6.7 Unit ns ns ns NOTE SDRAM CLK and DQS related parameters are being measured from the 50% point--that is, high is defined as 50% of signal value and low is defined as 50% of signal value. 4.3.10 ETM Electrical Specifications ETM is an ARM protocol. There are no inherent restrictions on operating frequency, other than ASIC pad technology and TPA limitations. ASIC designers must provide a TRACECLK as symmetrical as possible, and with set-up and hold times as large as possible. TPA designers must conversely be able to support a TRACECLK as asymmetrical as possible, and require set up and hold times as short as possible. The timing specifications in this section are given as a guide for a TPA that supports TRACECLK frequencies up to around 100 MHz. NOTE Actual processor clock frequencies vary according to application requirements and the silicon process technologies used. The maximum operating clock frequencies attained by ARM devices increases over time as a result. If a designer adheres to the timing described here, he or she can use any ARM-approved TPA. Figure 42 depicts the TRACECLK timings of ETM, and Table 40 lists the timing parameters. i.MX31/i.MX31L Advance Information, Rev. 1.4 100 Preliminary Freescale Semiconductor Electrical Characteristics Figure 42. ETM TRACECLK Timing Diagram Table 40. ETM TRACECLK Timing Parameters ID Tcyc Twl Twh Tr Tf Clock period Low pulse width High pulse width Clock and data rise time Clock and data fall time Parameter Min Frequency dependent 2 2 - - Max - - - 3 3 Unit ns ns ns ns ns Figure 43 depicts the setup and hold requirements of the trace data pins with respect to TRACECLK, and Table 41 lists the timing parameters. Figure 43. Trace Data Timing Diagram Table 41. ETM Trace Data Timing Parameters ID Ts Th Data setup Data hold Parameter Min 2 1 Max - - Unit ns ns 4.3.10.1 Half-Rate Clocking Mode When half-rate clocking is used, the trace data signals are sampled by the TPA on both the rising and falling edges of TRACECLK, where TRACECLK is half the frequency of the clock shown in Figure 43. 4.3.11 FIR Electrical Specifications FIR implements asynchronous infrared protocols (FIR, MIR) that are defined by IrDA(R) (Infrared Data Association). Refer to http://www.IrDA.org for details on FIR and MIR protocols. i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 101 Electrical Characteristics 4.3.12 Fusebox Electrical Specifications Table 42. Fusebox Supply Current Parameters Ref. Num 1 Description eFuse Program Current.1 Current to program one eFuse bit efuse_pgm = 3.0V eFuse Read Current2 Current to read an 8-bit eFuse word vdd_fusebox = 1.875V Symbol Minimum Typical Maximum Units Iprogram - 35 60 mA 2 Iread - 5 8 mA 1 2 The current Iprogram is during program time (tprogram). The current Iread is present for approximately 50nS of the read access to the 8 bit word Table 43. Fusebox Timing Characteristics Ref. Num 1 1 Description Program time for eFuse1 Symbol tprogram Minimum 125 Typical - Maximum - Units s The program length is defined by the value defined in the epm_pgm_length[2:0] bits of the IIM module. The value to program is based on a 32 kHz clock source (4 * 1/32 kHz = 125 s) 4.3.13 I2C Electrical Specifications This section describes the electrical information of the I2C Module. 4.3.13.1 I2C Module Timing Figure 44 depicts the timing of I2C module. Table 44 lists the I2C module timing parameters where the I/O supply is 2.7 V. 1 I2DAT IC10 IC11 IC9 I2CLK IC2 IC8 IC4 IC7 IC3 START IC10 IC6 IC1 IC5 IC11 START STOP START Figure 44. I2C Bus Timing Diagram i.MX31/i.MX31L Advance Information, Rev. 1.4 102 Preliminary Freescale Semiconductor Electrical Characteristics Table 44. I2C Module Timing Parameters--I2C Pin I/O Supply=2.7 V Standard Mode ID Parameter Min IC1 IC2 IC3 IC4 IC5 IC6 IC7 IC8 IC9 IC10 IC11 IC12 1 Fast Mode Unit Min 2.5 0.6 0.6 01 0.6 1.3 0.6 1003 1.3 20+0.1Cb4 20+0.1Cb4 - Max - - - 0.92 - - - - - 300 300 400 s s s s s s s ns s ns ns pF Max - - - 3.452 - - - - - 1000 300 400 I2CLK cycle time Hold time (repeated) START condition Set-up time for STOP condition Data hold time HIGH Period of I2CLK Clock LOW Period of the I2CLK Clock Set-up time for a repeated START condition Data set-up time Bus free time between a STOP and START condition Rise time of both I2DAT and I2CLK signals Fall time of both I2DAT and I2CLK signals Capacitive load for each bus line (Cb) 10 4.0 4.0 01 4.0 4.7 4.7 250 4.7 - - - A device must internally provide a hold time of at least 300 ns for I2DAT signal in order to bridge the undefined region of the falling edge of I2CLK. 2 The maximum hold time has to be met only if the device does not stretch the LOW period (ID IC6) of the I2CLK signal. 3 A Fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement of set-up time (ID IC7) of 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the I2CLK signal. If such a device does stretch the LOW period of the I2CLK signal, it must output the next data bit to the I2DAT line max_rise_time (ID No IC10) + data_setup_time (ID No IC8) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the I2CLK line is released. 4 Cb = total capacitance of one bus line in pF. 4.3.14 4.3.14.1 IPU--Sensor Interfaces Supported Sensors Table 45. Supported Camera Sensors Vendor Conexant Agilant Toshiba ICMedia iMagic Transchip CX11646, CX20490, CX20450 HDCP-2010, ADCS-1021, ADCS-1021 TC90A70 ICM202A, ICM102 IM8801 TC5600, TC5600J, TC5640, TC5700, TC6000 Model Table 45 lists the supported camera sensors by vendor and model. i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 103 Electrical Characteristics Table 45. Supported Camera Sensors (continued) Vendor Fujitsu Micron Matsushita STMicro OmniVision Sharp Motorola National Semiconductor MB86S02A MI-SOC-0133 MN39980 W6411, W6500, W6501, W6600, W6552, STV0974 OV7620, OV6630 LZ0P3714 (CCD) MC30300 (Python), SCM20014, SCM20114, SCM22114, SCM20027 LM9618 Model 4.3.14.2 Functional Description There are three timing modes supported by the IPU. 4.3.14.2.1 Pseudo BT.656 Video Mode Smart camera sensors, which include imaging processing, usually support video mode transfer. They use an embedded timing syntax to replace the SENSB_VSYNC and SENSB_HSYNC signals. The timing syntax is defined by the BT.656 standard. This operation mode follows the recommendations of ITU BT.656 specifications. The only control signal used is SENSB_PIX_CLK. Start-of-frame and active-line signals are embedded in the data stream. An active line starts with a SAV code and ends with a EAV code. In some cases, digital blanking is inserted in between EAV and SAV code. The CSI decodes and filters out the timing-coding from the data stream, thus recovering SENSB_VSYNC and SENSB_HSYNC signals for internal use. 4.3.14.2.2 Gated Clock Mode The SENSB_VSYNC, SENSB_HSYNC, and SENSB_PIX_CLK signals are used in this mode. See Figure 45. i.MX31/i.MX31L Advance Information, Rev. 1.4 104 Preliminary Freescale Semiconductor Electrical Characteristics Active Line nth frame n+1th frame Start of Frame SENSB_VSYNC SENSB_HSYNC SENSB_PIX_CLK SENSB_DATA[9:0] invalid invalid 1st byte 1st byte Figure 45. Gated Clock Mode Timing Diagram A frame starts with a rising edge on SENSB_VSYNC (all the timings correspond to straight polarity of the corresponding signals). Then SENSB_HSYNC goes to high and hold for the entire line. Pixel clock is valid as long as SENSB_HSYNC is high. Data is latched at the rising edge of the valid pixel clocks. SENSB_HSYNC goes to low at the end of line. Pixel clocks then become invalid and the CSI stops receiving data from the stream. For next line the SENSB_HSYNC timing repeats. For next frame the SENSB_VSYNC timing repeats. 4.3.14.2.3 Non-Gated Clock Mode The timing is the same as the gated-clock mode (described in Section 4.3.14.2.2, "Gated Clock Mode" on page 104), except for the SENSB_HSYNC signal, which is not used. See Figure 46. All incoming pixel clocks are valid and will cause data to be latched into the input FIFO. The SENSB_PIX_CLK signal is inactive (states low) until valid data is going to be transmitted over the bus. Start of Frame nth frame n+1th frame SENSB_VSYNC SENSB_PIX_CLK SENSB_DATA[7:0] invalid invalid 1st byte 1st byte Figure 46. Non-Gated Clock Mode Timing Diagram The timing described in Figure 46 is that of a Motorola sensor. Some other sensors may have a slightly different timing. The CSI can be programmed to support rising/falling-edge triggered SENSB_VSYNC; active-high/low SENSB_HSYNC; and rising/falling-edge triggered SENSB_PIX_CLK. i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 105 Electrical Characteristics 4.3.14.3 Electrical Characteristics Figure 47 depicts the sensor interface timing, and Table 46 lists the timing parameters. 1/IP1 SENSB_MCLK (Sensor Input) SENSB_PIX_CLK (Sensor Output) IP3 SENSB_DATA, SENSB_VSYNC, SENSB_HSYNC IP2 1/IP4 Figure 47. Sensor Interface Timing Diagram Table 46. Sensor Interface Timing Parameters ID IP1 IP2 IP3 IP4 Parameter Sensor input clock frequency Data and control setup time Data and control holdup time Sensor output (pixel) clock frequency Symbol Fmck Tsu Thd Fpck Min. 0.01 5 3 0.01 Max. 133 - - 133 Units MHz ns ns MHz 4.3.15 4.3.15.1 IPU--Display Interfaces Supported Displays Table 47. Supported Displays Type Vendor Sharp (HR-TFT Super Mobile LCD family) Samsung (QSIF and QVGA TFT modules for mobile phones) Toshiba (LTM series) Model LQ035Q7 DB02, LM019LC1Sxx LTS180S1-HF1, LTS180S3-HF1, LTS350Q1-PE1, LTS350Q1-PD1, LTS220Q1-HE1 LTM022P806, LTM04C380K, LTM018A02A, LTM020P332, LTM021P337, LTM019P334, LTM022A783, LTM022A05ZZ Table 47 lists the supported displays by type, vendor, and model. TFT displays (memory-less) i.MX31/i.MX31L Advance Information, Rev. 1.4 106 Preliminary Freescale Semiconductor Electrical Characteristics Table 47. Supported Displays (continued) Type Display controllers Epson Solomon Systech Hitachi ATI Smart display modules Epson Hitachi Densitron Europe LTD Sharp Sony Digital video encoders (for TV) Analog Devices Crystal (Cirrus Logic) Focus Vendor Model S1D15xxx series, S1D19xxx series, S1D13713, S1D13715 SSD1301 (OLED), SSD1828 (LDCD) HD66766, HD66772 W2300 L1F10043 T, L1F10044 T, L1F10045 T, L2D22002, L2D20014, L2F50032, L2D25001 T 120 160 65K/4096 C-STN (#3284 LTD-1398-2) based on HD 66766 controller All displays with MPU 80/68K series interface and serial peripheral interface LM019LC1Sxx ACX506AKM ADV7174/7179 CS49xx series FS453/4 4.3.15.2 4.3.15.2.1 Synchronous Interfaces Interface to Active Matrix TFT LCD Panels, Functional Description Figure 48 depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure signals are shown with negative polarity. The sequence of events for active matrix interface timing is: * DISPB_D3_CLK latches data into the panel on its negative edge (when positive polarity is selected). In active mode, DISPB_D3_CLK runs continuously. This signal frequency could be from 5 to 10 MHz depending on the panel type. * DISPB_D3_HSYNC causes the panel to start a new line. * DISPB_D3_VSYNC causes the panel to start a new frame. It always encompasses at least one HSYNC pulse. * DISPB_D3_DRDY acts like an output enable signal to the CRT display. This output enables the data to be shifted onto the display. When disabled, the data is invalid and the trace is off. i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 107 Electrical Characteristics DISPB_D3_VSYNC DISPB_D3_HSYNC LINE 1 LINE 2 LINE 3 LINE 4 LINE n-1 LINE n DISPB_D3_HSYNC DISPB_D3_DRDY 1 DISPB_D3_CLK DISPB_D3_DATA 2 3 m-1 m Figure 48. Interface Timing Diagram for TFT (Active Matrix) Panels 4.3.15.2.2 Interface to Active Matrix TFT LCD Panels, Electrical Characteristics Figure 49 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and the data. All figure parameters shown are programmable. The timing images correspond to inverse polarity of the DISPB_D3_CLK signal and active-low polarity of the DISPB_D3_HSYNC, DISPB_D3_VSYNC and DISPB_D3_DRDY signals. IP7 IP9 IP8 Start of line IP5 IP6 IP10 DISPB_D3_CLK DISPB_D3_HSYNC DISPB_D3_DRDY DISPB_D3_DATA Figure 49. TFT Panels Timing Diagram--Horizontal Sync Pulse Figure 50 depicts the vertical timing (timing of one frame). All figure parameters shown are programmable. i.MX31/i.MX31L Advance Information, Rev. 1.4 108 Preliminary Freescale Semiconductor Electrical Characteristics Start of frame IP13 DISPB_D3_VSYNC End of frame DISPB_D3_HSYNC DISPB_D3_DRDY IP11 IP14 IP12 IP15 Figure 50. TFT Panels Timing Diagram--Vertical Sync Pulse Table 48 shows timing parameters of signals presented in Figure 49 and Figure 50. Table 48. Synchronous Display Interface Timing Parameters--Pixel Level ID IP5 IP6 IP7 IP8 IP9 IP10 IP12 IP13 Parameter Display interface clock period Display pixel clock period Screen width HSYNC width Horizontal blank interval 1 Horizontal blank interval 2 Screen height VSYNC width Symbol Tdicp Tdpcp Tsw Thsw Thbi1 Thbi2 Tsh Tvsw ( 1) (DISP3_IF_CLK_CNT_D+1) * Tdicp (SCREEN_WIDTH+1) * Tdpcp (H_SYNC_WIDTH+1) * Tdpcp BGXP * Tdpcp (SCREEN_WIDTH - BGXP - FW) * Tdpcp (SCREEN_HEIGHT+1) * Tsw if V_SYNC_WIDTH_L = 0 than (V_SYNC_WIDTH+1) * Tdpcp else (V_SYNC_WIDTH+1) * Tsw BGYP * Tsw (SCREEN_HEIGHT - BGYP - FH) * Tsw Value Units ns ns ns ns ns ns ns ns IP14 IP15 1 Vertical blank interval 1 Vertical blank interval 2 Tvbi1 Tvbi2 ns ns Display interface clock period immediate value. DISP3_IF_CLK_PER_WR T HSP_CLK ----------------------------------------------------------------- , HSP_CLK_PERIOD Tdicp = DISP3_IF_CLK_PER_WR T floor ----------------------------------------------------------------- + 0.5 0.5 , HSP_CLK HSP_CLK_PERIOD DISP3_IF_CLK_PER_WR for integer ----------------------------------------------------------------HSP_CLK_PERIOD DISP3_IF_CLK_PER_WR for fractional ----------------------------------------------------------------HSP_CLK_PERIOD Display interface clock period average value. DISP3_IF_CLK_PER_WR Tdicp = T HSP_CLK ----------------------------------------------------------------HSP_CLK_PERIOD i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 109 Electrical Characteristics The SCREEN_WIDTH, SCREEN_HEIGHT, H_SYNC_WIDTH, V_SYNC_WIDTH, BGXP, BGYP and V_SYNC_WIDTH_L parameters are programmed via the SDC_HOR_CONF, SDC_VER_CONF, SDC_BG_POS Registers. The FW and FH parameters are programmed for the corresponding DMA channel. The DISP3_IF_CLK_PER_WR, HSP_CLK_PERIOD and DISP3_IF_CLK_CNT_D parameters are programmed via the DI_DISP3_TIME_CONF, DI_HSP_CLK_PER and DI_DISP_ACC_CC Registers. Figure 51 depicts the synchronous display interface timing for access level, and Table 49 lists the timing parameters. The DISP3_IF_CLK_DOWN_WR and DISP3_IF_CLK_UP_WR parameters are set via the DI_DISP3_TIME_CONF Register. DISPB_D3_VSYNC DISPB_D3_HSYNC DISPB_D3_DRDY other controls DISPB_D3_CLK IP20 IP16 DISPB_DATA IP17 IP19 IP18 Figure 51. Synchronous Display Interface Timing Diagram--Access Level Table 49. Synchronous Display Interface Timing Parameters--Access Level ID IP16 IP17 IP18 IP19 IP20 Parameter Display interface clock low time Display interface clock high time Data setup time Data holdup time Control signals setup time to display interface clock Symbol Tckl Tckh Tdsu Tdhd Tcsu Min Tdicd-Tdicu-1.5 Tdicp-Tdicd+Tdicu-1.5 Tdicd-3.5 Tdicp-Tdicd-3.5 Tdicd-3.5 Typ1 Tdicd2-Tdicu3 Tdicp-Tdicd+Tdicu Tdicu Tdicp-Tdicu Tdicu Max Tdicd-Tdicu+1.5 Tdicp-Tdicd+Tdicu+1.5 - Units ns ns ns ns ns The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These conditions may be chip specific. 2 Display interface clock down time 1 2 DISP3_IF_CLK_DOWN_WR Tdicd = -- T HSP_CLK ceil -------------------------------------------------------------------------------2 HSP_CLK_PERIOD 3 1 Display interface clock up time 1 2 DISP3_IF_CLK_UP_WR Tdicu = -- T HSP_CLK ceil --------------------------------------------------------------------2 HSP_CLK_PERIOD where CEIL(X) rounds the elements of X to the nearest integers towards infinity. i.MX31/i.MX31L Advance Information, Rev. 1.4 110 Preliminary Freescale Semiconductor Electrical Characteristics 4.3.15.3 Interface to Sharp HR-TFT Panels Figure 52 depicts the Sharp HR-TFT panel interface timing, and Table 50 lists the timing parameters. The CLS_RISE_DELAY, CLS_FALL_DELAY, PS_FALL_DELAY, PS_RISE_DELAY, REV_TOGGLE_DELAY parameters are defined in the SDC_SHARP_CONF_1 and SDC_SHARP_CONF_2 registers. For other Sharp interface timing characteristics, refer to Section 4.3.15.2.2, "Interface to Active Matrix TFT LCD Panels, Electrical Characteristics" on page 108. The timing images correspond to straight polarity of the Sharp signals. Horizontal timing DISPB_D3_CLK DISPB_D3_DATA D1 D2 D320 DISPB_D3_SPL IP21 1 DISPB_D3_CLK period DISPB_D3_HSYNC IP23 IP22 DISPB_D3_CLS IP24 DISPB_D3_PS IP25 IP26 DISPB_D3_REV Example is drawn with FW+1=320 pixel/line, FH+1=240 lines. SPL pulse width is fixed and aligned to the first data of the line. REV toggles every HSYNC period. Figure 52. Sharp HR-TFT Panel Interface Timing Diagram--Pixel Level Table 50. Sharp Synchronous Display Interface Timing Parameters--Pixel Level ID IP21 IP22 IP23 IP24 Parameter SPL rise time CLS rise time CLS fall time CLS rise and PS fall time Symbol Tsplr Tclsr Tclsf Tpsf (BGXP - 1) * Tdpcp CLS_RISE_DELAY * Tdpcp CLS_FALL_DELAY * Tdpcp PS_FALL_DELAY * Tdpcp Value Units ns ns ns ns i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 111 Electrical Characteristics Table 50. Sharp Synchronous Display Interface Timing Parameters--Pixel Level (continued) ID IP25 IP26 Parameter PS rise time REV toggle time Symbol Tpsr Trev Value PS_RISE_DELAY * Tdpcp REV_TOGGLE_DELAY * Tdpcp Units ns ns 4.3.15.4 Synchronous Interface to Dual-Port Smart Displays Functionality and electrical characteristics of the synchronous interface to dual-port smart displays are identical to parameters of the synchronous interface. See Section 4.3.15.2.2, "Interface to Active Matrix TFT LCD Panels, Electrical Characteristics" on page 108. 4.3.15.4.1 Interface to a TV Encoder, Functional Description The interface has an 8-bit data bus, transferring a single 8-bit value (Y/U/V) in each cycle. The bits D7-D0 of the value are mapped to bits LD17-LD10 of the data bus, respectively. Figure 53 depicts the interface timing, * The frequency of the clock DISPB_D3_CLK is 27 MHz (within 10%). * The DISPB_D3_HSYNC, DISPB_D3_VSYNC and DISPB_D3_DRDY signals are active low. * The transition to the next row is marked by the negative edge of the DISPB_D3_HSYNC signal. It remains low for a single clock cycle. * The transition to the next field/frame is marked by the negative edge of the DISPB_D3_VSYNC signal. It remains low for at least one clock cycle. -- At a transition to an odd field (of the next frame), the negative edges of DISPB_D3_VSYNC and DISPB_D3_HSYNC coincide. -- At a transition to an even field (of the same frame), they do not coincide. * The active intervals--during which data is transferred--are marked by the DISPB_D3_HSYNC signal being high. i.MX31/i.MX31L Advance Information, Rev. 1.4 112 Preliminary Freescale Semiconductor Electrical Characteristics DISPB_D3_CLK DISPB_D3_HSYNC DISPB_D3_VSYNC DISPB_D3_DRDY DISPB_DATA Cb Y Cr Y Cb Y Cr Pixel Data Timing DISPB_D3_HSYNC DISPB_D3_DRDY DISPB_D3_VSYNC 523 524 525 1 2 3 4 5 6 10 Even Field 261 DISPB_D3_HSYNC DISPB_D3_DRDY DISPB_D3_VSYNC 262 263 264 265 266 267 Odd Field 268 269 273 Odd Field Even Field Line and Field Timing - NTSC DISPB_D3_HSYNC DISPB_D3_DRDY DISPB_D3_VSYNC Even Field 621 622 623 624 625 1 2 3 4 23 Odd Field 308 DISPB_D3_HSYNC DISPB_D3_DRDY DISPB_D3_VSYNC 309 310 311 312 313 314 315 316 336 Odd Field Line and Field Timing - PAL Even Field Figure 53. TV Encoder Interface Timing Diagram i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 113 Electrical Characteristics 4.3.15.4.2 Interface to a TV Encoder, Electrical Characteristics The timing characteristics of the TV encoder interface are identical to the synchronous display characteristics. See Section 4.3.15.2.2, "Interface to Active Matrix TFT LCD Panels, Electrical Characteristics" on page 108. 4.3.15.5 4.3.15.5.1 Asynchronous Interfaces Parallel Interfaces, Functional Description The IPU supports the following asynchronous parallel interfaces: * System 80 interface -- Type 1 (sampling with the chip select signal) with and without byte enable signals. -- Type 2 (sampling with the read and write signals) with and without byte enable signals. * System 68k interface -- Type 1 (sampling with the chip select signal) with or without byte enable signals. -- Type 2 (sampling with the read and write signals) with or without byte enable signals. For each of four system interfaces, there are three burst modes: 1. Burst mode without a separate clock. The burst length is defined by the corresponding parameters of the IDMAC (when data is transferred from the system memory) of by the HBURST signal (when the MCU directly accesses the display via the slave AHB bus). For system 80 and system 68k type 1 interfaces, data is sampled by the CS signal and other control signals changes only when transfer direction is changed during the burst. For type 2 interfaces, data is sampled by the WR/RD signals (system 80) or by the ENABLE signal (system 68k) and the CS signal stays active during the whole burst. 2. Burst mode with the separate clock DISPB_BCLK. In this mode, data is sampled with the DISPB_BCLK clock. The CS signal stays active during whole burst transfer. Other controls are changed simultaneously with data when the bus state (read, write or wait) is altered. The CS signals and other controls move to non-active state after burst has been completed. 3. Single access mode. In this mode, slave AHB and DMA burst are broken to single accesses. The data is sampled with CS or other controls according the interface type as described above. All controls (including CS) become non-active for one display interface clock after each access. This mode corresponds to the ATI single access mode. Both system 80 and system 68k interfaces are supported for all described modes as depicted in Figure 54, Figure 55, Figure 56, and Figure 57. These timing images correspond to active-low DISPB_D#_CS, DISPB_D#_WR and DISPB_D#_RD signals. Additionally, the IPU allows a programmable pause between two burst. The pause is defined in the HSP_CLK cycles. It allows to avoid timing violation between two sequential bursts or two accesses to different displays. The range of this pause is from 4 to 19 HSP_CLK cycles. i.MX31/i.MX31L Advance Information, Rev. 1.4 114 Preliminary Freescale Semiconductor Electrical Characteristics DISPB_D#_CS DISPB_PAR_RS DISPB_WR DISPB_RD DISPB_DATA Burst access mode with sampling by CS signal DISPB_BCLK DISPB_D#_CS DISPB_PAR_RS DISPB_WR DISPB_RD DISPB_DATA Burst access mode with sampling by separate burst clock (BCLK) DISPB_D#_CS DISPB_PAR_RS DISPB_WR DISPB_RD DISPB_DATA Single access mode (all control signals are not active for one display interface clock after each display access) Figure 54. Asynchronous Parallel System 80 Interface (Type 1) Burst Mode Timing Diagram i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 115 Electrical Characteristics DISPB_D#_CS DISPB_PAR_RS DISPB_WR DISPB_RD DISPB_DATA Burst access mode with sampling by WR/RD signals DISPB_BCLK DISPB_D#_CS DISPB_PAR_RS DISPB_WR DISPB_RD DISPB_DATA Burst access mode with sampling by separate burst clock (BCLK) DISPB_D#_CS DISPB_PAR_RS DISPB_WR DISPB_RD DISPB_DATA Single access mode (all control signals are not active for one display interface clock after each display access) Figure 55. Asynchronous Parallel System 80 Interface (Type 2) Burst Mode Timing Diagram i.MX31/i.MX31L Advance Information, Rev. 1.4 116 Preliminary Freescale Semiconductor Electrical Characteristics DISPB_D#_CS DISPB_PAR_RS DISPB_WR (READ/WRITE) DISPB_RD (ENABLE) DISPB_DATA Burst access mode with sampling by CS signal DISPB_BCLK DISPB_D#_CS DISPB_PAR_RS DISPB_WR (READ/WRITE) DISPB_RD (ENABLE) DISPB_DATA Burst access mode with sampling by separate burst clock (BCLK) DISPB_D#_CS DISPB_PAR_RS DISPB_WR (READ/WRITE) DISPB_RD (ENABLE) DISPB_DATA Single access mode (all control signals are not active for one display interface clock after each display access) Figure 56. Asynchronous Parallel System 68k Interface (Type 1) Burst Mode Timing Diagram i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 117 Electrical Characteristics DISPB_D#_CS DISPB_PAR_RS DISPB_WR (READ/WRITE) DISPB_RD (ENABLE) DISPB_DATA Burst access mode with sampling by ENABLE signal DISPB_BCLK DISPB_D#_CS DISPB_PAR_RS DISPB_WR (READ/WRITE) DISPB_RD (ENABLE) DISPB_DATA Burst access mode with sampling by separate burst clock (BCLK) DISPB_D#_CS DISPB_PAR_RS DISPB_WR (READ/WRITE) DISPB_RD (ENABLE) DISPB_DATA Single access mode (all control signals are not active for one display interface clock after each display access) Figure 57. Asynchronous Parallel System 68k Interface (Type 2) Burst Mode TIming Diagram Display read operation can be performed with wait states when each read access takes up to 4 display interface clock cycles according to the DISP0_RD_WAIT_ST parameter in the DI_DISP0_TIME_CONF_3, DI_DISP1_TIME_CONF_3, DI_DISP2_TIME_CONF_3 Registers. Figure 58 shows timing of the parallel interface with read wait states. i.MX31/i.MX31L Advance Information, Rev. 1.4 118 Preliminary Freescale Semiconductor Electrical Characteristics WRITE OPERATION DISP0_RD_WAIT_ST=00 READ OPERATION DISPB_D#_CS DISPB_RD DISPB_WR DISPB_PAR_RS DISPB_DATA DISP0_RD_WAIT_ST=01 DISPB_D#_CS DISPB_RD DISPB_WR DISPB_PAR_RS DISPB_DATA DISP0_RD_WAIT_ST=10 DISPB_D#_CS DISPB_RD DISPB_WR DISPB_PAR_RS DISPB_DATA Figure 58. Parallel Interface Timing Diagram--Read Wait States 4.3.15.5.2 Parallel Interfaces, Electrical Characteristics Figure 59, Figure 61, Figure 60, and Figure 62 depict timing of asynchronous parallel interfaces based on the system 80 and system 68k interfaces. Table 51 lists the timing parameters at display access level. All timing images are based on active low control signals (signals polarity is controlled via the DI_DISP_SIG_POL Register). i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 119 Electrical Characteristics IP28, IP27 DISPB_PAR_RS DISPB_RD (READ_L) DISPB_DATA[17] (READ_H) IP35, IP33 DISPB_D#_CS IP36, IP34 DISPB_WR (WRITE_L) DISPB_DATA[16] (WRITE_H) IP31, IP29 read point IP37 DISPB_DATA (Input) Read Data IP38 IP32, IP30 IP39 DISPB_DATA (Output) IP40 IP46,IP44 IP47 IP45, IP43 IP42, IP41 Figure 59. Asynchronous Parallel System 80 Interface (Type 1) Timing Diagram i.MX31/i.MX31L Advance Information, Rev. 1.4 120 Preliminary Freescale Semiconductor Electrical Characteristics IP28, IP27 DISPB_PAR_RS DISPB_D#_CS IP35, IP33 DISPB_RD (READ_L) DISPB_DATA[17] (READ_H) DISPB_WR (WRITE_L) DISPB_DATA[16] (WRITE_H) IP31, IP29 read point IP37 DISPB_DATA (Input) IP39 DISPB_DATA (Output) Read Data IP38 IP36, IP34 IP32, IP30 IP40 IP46,IP44 IP47 IP45, IP43 IP42, IP41 Figure 60. Asynchronous Parallel System 80 Interface (Type 2) Timing Diagram i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 121 Electrical Characteristics IP28, IP27 DISPB_PAR_RS DISPB_RD (ENABLE_L) DISPB_DATA[17] (ENABLE_H) IP35,IP33 DISPB_D#_CS IP36, IP34 DISPB_WR (READ/WRITE) IP31, IP29 read point IP37 DISPB_DATA (Input) IP39 DISPB_DATA (Output) Read Data IP38 IP32, IP30 IP40 IP46,IP44 IP47 IP45, IP43 IP42, IP41 Figure 61. Asynchronous Parallel System 68k Interface (Type 1) Timing Diagram i.MX31/i.MX31L Advance Information, Rev. 1.4 122 Preliminary Freescale Semiconductor Electrical Characteristics IP28, IP27 DISPB_PAR_RS DISPB_D#_CS IP35,IP33 DISPB_RD (ENABLE_L) DISPB_DATA[17] (ENABLE_H) DISPB_WR (READ/WRITE) IP31, IP29 read point IP37 DISPB_DATA (Input) IP39 DISPB_DATA (Output) Read Data IP38 IP36, IP34 IP32, IP30 IP40 IP46,IP44 IP47 IP45, IP43 IP42, IP41 Figure 62. Asynchronous Parallel System 68k Interface (Type 2) Timing Diagram Table 51. Asynchronous Parallel Interface Timing Parameters--Access Level ID Parameter Symbol Tcycr Tcycw Trl Trh Twl Twh Tdcsr Tdchr Tdcsw Tdicpr-1.5 Tdicpw-1.5 Tdicdr-Tdicur-1.5 Tdicpr-Tdicdr+Tdicur-1.5 Tdicdw-Tdicuw-1.5 Tdicpw-Tdicdw+ Tdicuw-1.5 Tdicur-1.5 Tdicpr-Tdicdr-1.5 Tdicuw-1.5 Min. Typ.1 Tdicpr2 Tdicpw 3 Max. Tdicpr+1.5 Tdicpw+1.5 Tdicdr-Tdicur+1.5 Tdicpr-Tdicdr+Tdicur+1.5 Units ns ns ns ns ns ns ns ns ns IP27 Read system cycle time IP28 Write system cycle time IP29 Read low pulse width IP30 Read high pulse width IP31 Write low pulse width IP32 Write high pulse width IP33 Controls setup time for read IP34 Controls hold time for read IP35 Controls setup time for write Tdicdr4-Tdicur5 Tdicpr-Tdicdr+ Tdicur Tdicdw6-Tdicuw7 Tdicdw-Tdicuw+1.5 Tdicpw-Tdicdw+ Tdicuw Tdicur Tdicpr-Tdicdr Tdicuw Tdicpw-Tdicdw+ Tdicuw+1.5 - - - i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 123 Electrical Characteristics Table 51. Asynchronous Parallel Interface Timing Parameters--Access Level (continued) ID Parameter Symbol Tdchw Tracc 8 Min. Tdicpw-Tdicdw-1.5 0 Tdrp-Tlbd-Tdicdr+1.5 Tdicdw-1.5 Tdicpw-Tdicdw-1.5 Tdicpr-1.5 Typ.1 Tdicpw-Tdicdw - - Tdicdw Tdicpw-Tdicdw Tdicpr Tdicpw Tdicdr Tdicur Tdicdw Tdicuw Tdrp Max. - Tdrp9-Tlbd10-Tdicur-1.5 Tdicpr-Tdicdr-1.5 - - Tdicpr+1.5 Tdicpw+1.5 Tdicdr+1.5 Tdicur+1.5 Tdicdw+1.5 Tdicuw+1.5 Tdrp+1.5 Units ns ns ns ns ns ns ns ns ns ns ns ns IP36 Controls hold time for write IP37 Slave device data delay8 IP38 Slave device data hold time IP39 Write data setup time IP40 Write data hold time IP41 Read IP42 Write period2 period3 time4 5 Troh Tds Tdh Tdicpr Tdicpw Tdicpw-1.5 Tdicdr Tdicur Tdicdr-1.5 Tdicur-1.5 IP43 Read down IP44 Read up time IP45 Write down IP46 Write up time6 9 Tdicdw Tdicdw-1.5 Tdicuw Tdicuw-1.5 Tdrp Tdrp-1.5 time7 IP47 Read time point 1 The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These conditions may be chip specific. 2 Display interface clock period value for read: DISP#_IF_CLK_PER_RD Tdicpr = T HSP_CLK ceil --------------------------------------------------------------HSP_CLK_PERIOD 3Display interface clock period value for write: DISP#_IF_CLK_PER_WR Tdicpw = T HSP_CLK ceil ----------------------------------------------------------------HSP_CLK_PERIOD 4Display interface clock down time for read: 2 DISP#_IF_CLK_DOWN_RD 1 Tdicdr = -- T HSP_CLK ceil ------------------------------------------------------------------------------HSP_CLK_PERIOD 2 5Display interface clock up time for read: 1 2 DISP#_IF_CLK_UP_RD Tdicur = -- T HSP_CLK ceil -------------------------------------------------------------------HSP_CLK_PERIOD 2 6Display interface clock down time for write: 1 2 DISP#_IF_CLK_DOWN_WR Tdicdw = -- T HSP_CLK ceil -------------------------------------------------------------------------------HSP_CLK_PERIOD 2 7Display interface clock up time for write: 1 2 DISP#_IF_CLK_UP_WR Tdicuw = -- T HSP_CLK ceil --------------------------------------------------------------------2 HSP_CLK_PERIOD 8This 9 parameter is a requirement to the display connected to the IPU Data read point DISP#_READ_EN Tdrp = T HSP_CLK ceil ------------------------------------------------HSP_CLK_PERIOD 10Loopback delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a chip-level output delay, board delays, a chip-level input delay, an IPU input delay. This value is chip specific. i.MX31/i.MX31L Advance Information, Rev. 1.4 124 Preliminary Freescale Semiconductor Electrical Characteristics The DISP#_IF_CLK_PER_WR, DISP#_IF_CLK_PER_RD, HSP_CLK_PERIOD, DISP#_IF_CLK_DOWN_WR, DISP#_IF_CLK_UP_WR, DISP#_IF_CLK_DOWN_RD, DISP#_IF_CLK_UP_RD and DISP#_READ_EN parameters are programmed via the DI_DISP#_TIME_CONF_1, DI_DISP#_TIME_CONF_2 and DI_HSP_CLK_PER Registers. 4.3.15.5.3 Serial Interfaces, Functional Description The IPU supports the following types of asynchronous serial interfaces: * 3-wire (with bidirectional data line) * 4-wire (with separate data input and output lines) * 5-wire type 1 (with sampling RS by the serial clock) * 5-wire type 2 (with sampling RS by the chip select signal) Figure 63 depicts timing of the 3-wire serial interface. The timing images correspond to active-low DISPB_D#_CS signal and the straight polarity of the DISPB_SD_D_CLK signal. For this interface, a bidirectional data line is used outside the chip. The IPU still uses separate input and output data lines (IPP_IND_DISPB_SD_D and IPP_DO_DISPB_SD_D). The I/O mux should provide joining the internal data lines to the bidirectional external line according to the IPP_OBE_DISPB_SD_D signal provided by the IPU. Each data transfer can be preceded by an optional preamble with programmable length and contents. The preamble is followed by read/write (RW) and address (RS) bits. The order of the these bits is programmable. The RW bit can be disabled. The following data can consist of one word or of a whole burst. The interface parameters are controlled by the DI_SER_DISP1_CONF and DI_SER_DISP2_CONF Registers. DISPB_D#_CS 1 display IF clock cycle 1 display IF clock cycle DISPB_SD_D_CLK DISPB_SD_D RW RS D7 D6 D5 D4 D3 D2 D1 D0 Preamble Input or output data Figure 63. 3-wire Serial Interface Timing Diagram Figure 64 depicts timing of the 4-wire serial interface. For this interface, there are separate input and output data lines both inside and outside the chip. i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 125 Electrical Characteristics Write DISPB_D#_CS 1 display IF clock cycle 1 display IF clock cycle DISPB_SD_D_CLK DISPB_SD_D (Output) Preamble DISPB_SD_D (Input) RW RS D7 D6 D5 D4 D3 D2 D1 D0 Output data Read DISPB_D#_CS 1 display IF clock cycle 1 display IF clock cycle DISPB_SD_D_CLK DISPB_SD_D (Output) RW RS Preamble DISPB_SD_D (Input) D7 D6 D5 D4 D3 D2 D1 D0 Input data Figure 64. 4-wire Serial Interface Timing Diagram Figure 65 depicts timing of the 5-wire serial interface (Type 1). For this interface, a separate RS line is added. When a burst is transmitted within single active chip select interval, the RS can be changed at boundaries of words. i.MX31/i.MX31L Advance Information, Rev. 1.4 126 Preliminary Freescale Semiconductor Electrical Characteristics Write DISPB_D#_CS 1 display IF clock cycle 1 display IF clock cycle DISPB_SD_D_CLK DISPB_SD_D (Output) Preamble DISPB_SD_D (Input) DISPB_SER_RS RW D7 D6 D5 D4 D3 D2 D1 D0 Output data Read DISPB_D#_CS 1 display IF clock cycle 1 display IF clock cycle DISPB_SD_D_CLK DISPB_SD_D (Output) Preamble DISPB_SD_D (Input) D7 D6 D5 D4 D3 D2 D1 D0 RW Input data DISPB_SER_RS Figure 65. 5-wire Serial Interface (Type 1) Timing Diagram i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 127 Electrical Characteristics Figure 66 depicts timing of the 5-wire serial interface (Type 2). For this interface, a separate RS line is added. When a burst is transmitted within single active chip select interval, the RS can be changed at boundaries of words. Write DISPB_D#_CS 1 display IF clock cycle 1 display IF clock cycle DISPB_SD_D_CLK DISPB_SD_D (Output) RW D7 D6 D5 D4 D3 D2 D1 D0 Preamble DISPB_SD_D (Input) 1 display IF clock cycle Output data DISPB_SER_RS Read DISPB_D#_CS 1 display IF clock cycle 1 display IF clock cycle DISPB_SD_D_CLK DISPB_SD_D (Output) Preamble DISPB_SD_D (Input) D7 D6 D5 D4 D3 D2 D1 D0 RW DISPB_SER_RS 1 display IF clock cycle Input data Figure 66. 5-wire Serial Interface (Type 2) Timing Diagram i.MX31/i.MX31L Advance Information, Rev. 1.4 128 Preliminary Freescale Semiconductor Electrical Characteristics 4.3.15.5.4 Serial Interfaces, Electrical Characteristics Figure 67 depicts timing of the serial interface. Table 52 lists the timing parameters at display access level. IP49, IP48 DISPB_SER_RS IP56,IP54 IP57, IP55 DISPB_SD_D_CLK IP50, IP52 read point IP58 DISPB_DATA (Input) IP60 DISPB_DATA (Output) Read Data IP59 IP51, IP53 IP61 IP67,IP65 IP47 IP64, IP66 IP62, IP63 Figure 67. Asynchronous Serial Interface Timing Diagram Table 52. Asynchronous Serial Interface Timing Parameters--Access Level ID Parameter Symbol Tcycr Tcycw Trl Trh Twl Twh Tdcsr Tdchr Min. Tdicpr-1.5 Tdicpw-1.5 Tdicdr-Tdicur-1.5 Tdicpr-Tdicdr+Tdicur1.5 Tdicdw-Tdicuw-1.5 Tdicpw-Tdicdw+ Tdicuw-1.5 Tdicur-1.5 Tdicpr-Tdicdr-1.5 Typ.1 Tdicpr2 Tdicpw3 Tdicdr4-Tdicur5 Tdicpr-Tdicdr+ Tdicur Tdicdw6-Tdicuw7 Tdicpw-Tdicdw+ Tdicuw Tdicur Tdicpr-Tdicdr Max. Tdicpr+1.5 Tdicpw+1.5 Tdicdr-Tdicur+1.5 Tdicpr-Tdicdr+Tdicur+1.5 Tdicdw-Tdicuw+1.5 Tdicpw-Tdicdw+ Tdicuw+1.5 - - Units ns ns ns ns ns ns ns ns IP48 Read system cycle time IP49 Write system cycle time IP50 Read clock low pulse width IP51 Read clock high pulse width IP52 Write clock low pulse width IP53 Write clock high pulse width IP54 Controls setup time for read IP55 Controls hold time for read i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 129 Electrical Characteristics Table 52. Asynchronous Serial Interface Timing Parameters--Access Level (continued) ID Parameter Symbol Tdcsw Tdchw Tracc Troh Tds Tdh Tdicpr Tdicpw 4 Min. Tdicuw-1.5 Tdicpw-Tdicdw-1.5 0 Tdrp-Tlbd-Tdicdr+1.5 Tdicdw-1.5 Tdicpw-Tdicdw-1.5 Tdicpr-1.5 Tdicpw-1.5 Tdicdr-1.5 Tdicur-1.5 Tdicdw-1.5 Tdicuw-1.5 Tdrp-1.5 Tdicdw Tdicuw Typ.1 Max. - - Tdrp -Tlbd -Tdicur-1.5 Tdicpr-Tdicdr-1.5 - - Tdicpr+1.5 Tdicpw+1.5 Tdicdr+1.5 Tdicur+1.5 Tdicdw+1.5 Tdicuw+1.5 Tdrp+1.5 9 10 Units ns ns ns ns ns ns ns ns ns ns ns ns ns IP56 Controls setup time for write IP57 Controls hold time for write IP58 Slave device data delay IP59 Slave device data hold IP60 Write data setup time IP61 Write data hold time IP62 Read IP63 Write period2 period3 time5 time6 7 9 8 Tdicpw-Tdicdw - - time8 Tdicpw-Tdicdw Tdicpr Tdicpw Tdicdr Tdicur Tdicdw Tdicuw Tdrp IP64 Read down time IP65 Read up Tdicdr Tdicur Tdicdw Tdicuw Tdrp IP66 Write down IP67 Write up time IP68 Read time point 1 The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These conditions may be chip specific. 2 Display interface clock period value for read: DISP#_IF_CLK_PER_RD Tdicpr = T HSP_CLK ceil --------------------------------------------------------------HSP_CLK_PERIOD 3Display interface clock period value for write: DISP#_IF_CLK_PER_WR Tdicpw = T HSP_CLK ceil ----------------------------------------------------------------HSP_CLK_PERIOD 4 Display interface clock down time for read: 1 2 DISP#_IF_CLK_DOWN_RD Tdicdr = -- T HSP_CLK ceil ------------------------------------------------------------------------------HSP_CLK_PERIOD 2 5Display interface clock up time for read: 1 2 DISP#_IF_CLK_UP_RD Tdicur = -- T ceil -------------------------------------------------------------------2 HSP_CLK HSP_CLK_PERIOD 6 Display interface clock down time for write: 1 2 DISP#_IF_CLK_DOWN_WR Tdicdw = -- T ceil -------------------------------------------------------------------------------2 HSP_CLK HSP_CLK_PERIOD 7 Display interface clock up time for write: 1 2 DISP#_IF_CLK_UP_WR Tdicuw = -- T HSP_CLK ceil --------------------------------------------------------------------2 HSP_CLK_PERIOD 8 9Data This parameter is a requirement to the display connected to the IPU. read point: HSP_CLK DISP#_READ_EN ceil ------------------------------------------------HSP_CLK_PERIOD Tdrp = T 10Loopback delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a chip-level output delay, board delays, a chip-level input delay, an IPU input delay. This value is chip specific. i.MX31/i.MX31L Advance Information, Rev. 1.4 130 Preliminary Freescale Semiconductor Electrical Characteristics The DISP#_IF_CLK_PER_WR, DISP#_IF_CLK_PER_RD, HSP_CLK_PERIOD, DISP#_IF_CLK_DOWN_WR, DISP#_IF_CLK_UP_WR, DISP#_IF_CLK_DOWN_RD, DISP#_IF_CLK_UP_RD and DISP#_READ_EN parameters are programmed via the DI_DISP#_TIME_CONF_1, DI_DISP#_TIME_CONF_2 and DI_HSP_CLK_PER Registers. 4.3.16 Memory Stick Host Controller (MSHC) Figure 68, Figure 69, and Figure 70 depict the MSHC timings, and Table 53 and Table 54 list the timing parameters. tSCLKc tSCLKwh tSCLKwl MSHC_SCLK tSCLKr tSCLKf Figure 68. MSHC_CLK Timing Diagram tSCLKc MSHC_SCLK tBSsu tBSh MSHC_BS tDsu MSHC_DATA (Output) tDh tDd MSHC_DATA (Intput) Figure 69. Transfer Operation Timing Diagram (Serial) i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 131 Electrical Characteristics tSCLKc MSHC_SCLK tBSsu tBSh MSHC_BS tDsu MSHC_DATA (Output) tDh tDd MSHC_DATA (Intput) Figure 70. Transfer Operation Timing Diagram (Parallel) NOTE The Memory Stick Host Controller is designed to meet the timing requirements per Sony's Memory Stick Pro Format Specifications document. Tables in this section details the specifications requirements for parallel and serial modes, and not the i.MX31/i.MX31L timing. The timing will be provided once IC characterization is complete. Table 53. Serial Interface Timing Parameters Standards Signal Parameter Symbol Min. Cycle H pulse length MSHC_SCLK L pulse length Rise time Fall time Setup time MSHC_BS Hold time tBSh 5 - ns tSCLKc tSCLKwh tSCLKwl tSCLKr tSCLKf tBSsu 50 15 15 - - 5 Max. - - - 10 10 - ns ns ns ns ns ns Unit i.MX31/i.MX31L Advance Information, Rev. 1.4 132 Preliminary Freescale Semiconductor Electrical Characteristics Table 53. Serial Interface Timing Parameters (continued) Standards Signal Parameter Symbol Min. Setup time MSHC_DATA Hold time Output delay time tDsu tDh tDd 5 5 - Max. - - 15 ns ns ns Unit Table 54. Parallel Interface Timing Parameters Standards Signal Parameter Symbol Min Cycle H pulse length MSHC_SCLK L pulse length Rise time Fall time Setup time MSHC_BS Hold time Setup time MSHC_DATA Hold time Output delay time tBSh tDsu tDh tDd 1 8 1 - - - - 15 ns ns ns ns tSCLKc tSCLKwh tSCLKwl tSCLKr tSCLKf tBSsu 25 5 5 - - 8 Max - - - 10 10 - ns ns ns ns ns ns Unit 4.3.17 Personal Computer Memory Card International Association (PCMCIA) Figure 71 and Figure 72 depict the timings pertaining to the PCMCIA module, each of which is an example of one clock of strobe set-up time and one clock of strobe hold time. Table 55 lists the timing parameters. i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 133 Electrical Characteristics HCLK HADDR CONTROL HWDATA HREADY HRESP A[25:0] D[15:0] WAIT REG OE/WE/IORD/IOWR CE1/CE2 RD/WR POE REG OKAY ADDR 1 DATA write 1 OKAY OKAY ADDR 1 CONTROL 1 DATA write 1 PSST PSL PSHT Figure 71. Write Accesses Timing Diagram--PSHT=1, PSST=1 i.MX31/i.MX31L Advance Information, Rev. 1.4 134 Preliminary Freescale Semiconductor Electrical Characteristics HCLK HADDR CONTROL RWDATA HREADY HRESP A[25:0] D[15:0] WAIT REG OE/WE/IORD/IOWR CE1/CE2 RD/WR POE REG OKAY ADDR 1 OKAY OKAY ADDR 1 CONTROL 1 DATA read 1 PSST PSL PSHT Figure 72. Read Accesses Timing Diagram--PSHT=1, PSST=1 Table 55. PCMCIA Write and Read Timing Parameters Symbol PSHT PSST PSL Parameter PCMCIA strobe hold time PCMCIA strobe set up time PCMCIA strobe length Min 0 1 1 Max 63 63 128 Unit clock clock clock 4.3.18 PWM Electrical Specifications This section describes the electrical information of the PWM. The PWM can be programmed to select one of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before being input to the counter. The output is available at the pulse-width modulator output (PWMO) external pin. i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 135 Electrical Characteristics 4.3.18.1 PWM Timing Figure 73 depicts the timing of the PWM, and Table 56 lists the PWM timing characteristics. 2a System Clock 2b 3a 4a PWM Output 4b 1 3b Figure 73. PWM Timing Table 56. PWM Output Timing Parameters ID 1 2a 2b 3a 3b 4a 4b 1 Parameter System CLK frequency1 Clock high time Clock low time Clock fall time Clock rise time Output delay time Output setup time Min 0 12.29 9.91 - - - 8.71 Max ipg_clk - - 0.5 0.5 9.37 - Unit MHz ns ns ns ns ns ns CL of PWMO = 30 pF i.MX31/i.MX31L Advance Information, Rev. 1.4 136 Preliminary Freescale Semiconductor Electrical Characteristics 4.3.19 SDHC Electrical Specifications This section describes the electrical information of the SDHC. 4.3.19.1 SDHC Timing SD4 SD2 SD5 MMCx_CLK MMCx_CLK SD3 SD7 SD6 SD1 Figure 74 depicts the timings of the SDHC, and Table 57 lists the timing parameters. MMCx_CMD MMCx_DAT_0 output from SDHC to card MMCx_DAT_1 MMCx_DAT_2 MMCx_DAT_3 MMCx_CMD MMCx_DAT_0 MMCx_DAT_1 MMCx_DAT_2 MMCx_DAT_3 SD8 input from card to SDHC Figure 74. SDHC Timing Diagram . Table 57. SDHC Interface Timing Parameters ID Card Input Clock SD1 Clock Frequency (Low Speed) Clock Frequency (SD/SDIO Full Speed) Clock Frequency (MMC Full Speed) Clock Frequency (Identification Mode) SD2 SD3 SD4 SD5 Clock Low Time Clock High Time Clock Rise Time Clock Fall Time fPP1 fPP2 fPP3 fOD 4 Parameter Symbol Min Max Unit 0 0 0 100 10 10 - - 400 25 20 400 - - 10 10 kHz MHz MHz kHz ns ns ns ns tWL tWH tTLH tTHL SDHC output / Card Inputs CMD, DAT (Reference to CLK) SD6 SD7 SDHC output / Card input Set-up Time SDHC output / Card input Hold Time tISU tIH 5 5 - - ns ns i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 137 Electrical Characteristics Table 57. SDHC Interface Timing Parameters (continued) ID Parameter Symbol Min Max Unit SDHC input / Card Outputs CMD, DAT (Reference to CLK) SD8 Card Output Delay Time during Data Transfer Mode Output Delay time during Identification Mode 1 2 3 4 5 6 tODLY5 tODLY6 0 0 14 50 ns ns In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V. In normal data transfer mode for SD/SDIO card, clock frequency can be any value between 0 ~ 25 MHz. In normal data transfer mode for MMC card, clock frequency can be any value between 0 ~ 20 MHz. In card identification mode, card clock must be l100 kHz ~ 400 kHz, voltage ranges from 2.7 to 3.6 V. In identification mode, card output delay time should be less than 50 ns. In data transfer mode, card output delay time should be less than 14 ns. 4.3.20 SIM Electrical Specifications Each SIM card interface consist of a total of 12 pins (for 2 separate ports of 6 pins each. Mostly one port with 5 pins is used). The interface is meant to be used with synchronous SIM cards. This means that the SIM module provides a clock for the SIM card to use. The frequency of this clock is normally 372 times the data rate on the TX/RX pins, however SIM module can work with CLK equal to 16 times the data rate on TX/RX pins. There is no timing relationship between the clock and the data. The clock that the SIM module provides to the aim card will be used by the SIM card to recover the clock from the data much like a standard UART. All six (or 5 in case bi directional TXRX is used) of the pins for each half of the SIM module are asynchronous to each other. There are no required timing relationships between the pads in normal mode, but there are some in two specific cases: reset and power down sequences. 4.3.20.1 General Timing Requirements Figure 75 shows the timing of the SIM module, and Figure 58 lists the timing parameters. 1/Sfreq CLK Sfall Srise Figure 75. SIM Clock Timing Diagram i.MX31/i.MX31L Advance Information, Rev. 1.4 138 Preliminary Freescale Semiconductor Electrical Characteristics Table 58. SIM Timing Specification--High Drive Strength Num 1 2 3 4 1 2 Description SIM Clock Frequency (CLK)1 SIM CLK Rise Time 2 SIM CLK Fall Time 3 SIM Input Transition Time (RX, SIMPD) Symbol Sfreq Srise Sfall Strans Min 0.01 - - - Max 5 (Some new cards may reach 10) 20 20 25 Unit MHz ns ns ns 50% duty cycle clock With C = 50pF 3 With C = 50pF 4.3.20.2 4.3.20.2.1 Reset Sequence Cards with Internal Reset The sequence of reset for this kind of SIM Cards is as follows (see Figure 76): * After powerup, the clock signal is enabled on SGCLK (time T0) * After 200 clock cycles, RX must be high. * The card must send a response on RX acknowledging the reset between 400 and 40000 clock cycles after T0. SVEN CLK RX 1 2 response 1 T0 400 clock cycles < 2 < 200 clock cycles < 40000 clock cycles Figure 76. Internal-Reset Card Reset Sequence 4.3.20.2.2 Cards with Active Low Reset The sequence of reset for this kind of card is as follows (see Figure 77): 1. After powerup, the clock signal is enabled on CLK (time T0) 2. After 200 clock cycles, RX must be high. 3. RST must remain Low for at least 40000 clock cycles after T0 (no response is to be received on RX during those 40000 clock cycles) 4. RST is set High (time T1) i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 139 Electrical Characteristics 5. RST must remain High for at least 40000 clock cycles after T1 and a response must be received on RX between 400 and 40000 clock cycles after T1. SVEN RST CLK RX 1 2 response 3 T0 T1 3 1 400 clock cycles < 400000 clock cycles < 2 3 < 200 clock cycles < 40000 clock cycles Figure 77. Active-Low-Reset Card Reset Sequence 4.3.20.3 Power Down Sequence Power down sequence for SIM interface is as follows: 1. SIMPD port detects the removal of the SIM Card 2. RST goes Low 3. CLK goes Low 4. TX goes Low 5. VEN goes Low Each of this steps is done in one CKIL period (usually 32 kHz). Power down can be started because of a SIM Card removal detection or launched by the processor. Figure 78 and Table 59 show the usual timing requirements for this sequence, with Fckil = CKIL frequency value. i.MX31/i.MX31L Advance Information, Rev. 1.4 140 Preliminary Freescale Semiconductor Electrical Characteristics Spd2rst SIMPD RST Srst2clk CLK Srst2dat DATA_TX Srst2ven SVEN Figure 78. SmartCard Interface Power Down AC Timing Table 59. Timing Requirements for Power Down Sequence Num 1 2 3 4 Description SIM reset to SIM clock stop SIM reset to SIM TX data low SIM reset to SIM Voltage Enable Low SIM Presence Detect to SIM reset Low Symbol Srst2clk Srst2dat Srst2ven Spd2rst Min 0.9*1/FCKIL 1.8*1/FCKIL 2.7*1/FCKIL 0.9*1/FCKIL Max 0.8 1.2 1.8 25 Unit s s s ns 4.3.21 SJC Electrical Specifications This section details the electrical characteristics for the SJC module. Figure 79 depicts the SJC test clock input timing. Figure 80 depicts the SJC boundary scan timing, Figure 81 depicts the SJC test access port, Figure 82 depicts the SJC TRST timing, and Table 60 lists the SJC timing parameters. SJ1 SJ2 TCK (Input) VIH VIL SJ3 SJ3 VM SJ2 VM Figure 79. Test Clock Input Timing Diagram i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 141 Electrical Characteristics TCK (Input) VIL SJ4 Data Inputs SJ6 Data Outputs SJ7 Data Outputs SJ6 Data Outputs Output Data Valid Output Data Valid Input Data Valid VIH SJ5 Figure 80. Boundary Scan (JTAG) Timing Diagram TCK (Input) VIL SJ8 TDI TMS (Input) SJ10 TDO (Output) SJ11 TDO (Output) SJ10 TDO (Output) Output Data Valid Output Data Valid Input Data Valid SJ9 VIH Figure 81. Test Access Port Timing Diagram i.MX31/i.MX31L Advance Information, Rev. 1.4 142 Preliminary Freescale Semiconductor Electrical Characteristics TCK (Input) SJ13 TRST (Input) SJ12 Figure 82. TRST Timing Diagram Table 60. SJC Timing Parameters All Frequencies ID Parameter1 Min SJ1 SJ2 SJ3 SJ4 SJ5 SJ6 SJ7 SJ8 SJ9 TCK cycle time TCK clock pulse width measured at VM1 TCK rise and fall times Boundary scan input data set-up time Boundary scan input data hold time TCK low to output data valid TCK low to output high impedance TMS, TDI data set-up time TMS, TDI data hold time 100.0 40.0 - 10.0 50.0 - - 10.0 50.0 - - 100.0 40.0 Max - - 3.0 - - 40.0 40.0 - - 44.0 44.0 - - ns ns ns ns ns ns ns ns ns ns ns ns ns Unit SJ10 TCK low to TDO data valid SJ11 TCK low to TDO high impedance SJ12 TRST assert time SJ13 TRST set-up time to TCK low 1V M - mid point voltage 4.3.22 SSI Electrical Specifications This section describes the electrical information of SSI. 4.3.22.1 SSI Transmitter Timing with Internal Clock Figure 83 depicts the SSI transmitter timing with internal clock, and Table 61 lists the timing parameters. i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 143 Electrical Characteristics SS1 SS2 AD1_TXC (Output) SS6 AD1_TXFS (bl) (Output) SS10 AD1_TXFS (wl) (Output) SS16 AD1_TXD (Output) SS8 SS5 SS4 SS3 SS12 SS14 SS15 SS17 SS18 SS43 SS42 AD1_RXD (Input) Note: SRXD Input in Synchronous mode only SS1 SS2 SS19 SS5 SS4 SS3 DAM1_T_CLK (Output) SS6 DAM1_T_FS (bl) (Output) SS10 DAM1_T_FS (wl) (Output) SS16 DAM1_TXD (Output) SS43 SS42 DAM1_RXD (Input) Note: SRXD Input in Synchronous mode only SS19 SS14 SS15 SS17 SS18 SS12 SS8 Figure 83. SSI Transmitter with Internal Clock Timing Diagram i.MX31/i.MX31L Advance Information, Rev. 1.4 144 Preliminary Freescale Semiconductor Electrical Characteristics Table 61. SSI Transmitter with Internal Clock Timing Parameters ID Internal Clock Operation SS1 SS2 SS3 SS4 SS5 SS6 SS8 SS10 SS12 SS14 SS15 SS16 SS17 SS18 SS19 (Tx/Rx) CK clock period (Tx/Rx) CK clock high period (Tx/Rx) CK clock rise time (Tx/Rx) CK clock low period (Tx/Rx) CK clock fall time (Tx) CK high to FS (bl) high (Tx) CK high to FS (bl) low (Tx) CK high to FS (wl) high (Tx) CK high to FS (wl) low (Tx/Rx) Internal FS rise time (Tx/Rx) Internal FS fall time (Tx) CK high to STXD valid from high impedance (Tx) CK high to STXD high/low (Tx) CK high to STXD high impedance STXD rise/fall time 81.4 36.0 - 36.0 - - - - - - - - - - - - - 6 - 6 15.0 15.0 15.0 15.0 6 6 15.0 15.0 15.0 6 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Parameter Min Max Unit Synchronous Internal Clock Operation SS42 SS43 SS52 SRXD setup before (Tx) CK falling SRXD hold after (Tx) CK falling Loading 10.0 0 - - - 25 ns ns pF * * * * All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. All timings are on AUDMUX pads when SSI is being used for data transfer. "Tx" and "Rx" refer to the Transmit and Receive sections of the SSI. For internal Frame Sync operation using external clock, the FS timing will be same as that of Tx Data (for example, during AC97 mode of operation). i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 145 Electrical Characteristics 4.3.22.2 SSI Receiver Timing with Internal Clock Figure 84 depicts the SSI receiver timing with internal clock, and Table 62 lists the timing parameters. SS1 SS5 SS2 AD1_TXC (Output) SS7 AD1_TXFS (bl) (Output) AD1_TXFS (wl) (Output) SS20 SS21 AD1_RXD (Input) SS47 SS48 AD1_RXC (Output) SS51 SS50 SS49 SS9 SS4 SS3 SS11 SS13 SS1 SS5 SS2 SS4 SS3 DAM1_T_CLK (Output) SS7 DAM1_T_FS (bl) (Output) DAM1_T_FS (wl) (Output) SS20 SS21 DAM1_RXD (Input) SS47 SS48 DAM1_R_CLK (Output) SS51 SS50 SS49 SS9 SS11 SS13 Figure 84. SSI Receiver with Internal Clock Timing Diagram i.MX31/i.MX31L Advance Information, Rev. 1.4 146 Preliminary Freescale Semiconductor Electrical Characteristics Table 62. SSI Receiver with Internal Clock Timing Parameters ID Internal Clock Operation SS1 SS2 SS3 SS4 SS5 SS7 SS9 SS11 SS13 SS20 SS21 (Tx/Rx) CK clock period (Tx/Rx) CK clock high period (Tx/Rx) CK clock rise time (Tx/Rx) CK clock low period (Tx/Rx) CK clock fall time (Rx) CK high to FS (bl) high (Rx) CK high to FS (bl) low (Rx) CK high to FS (wl) high (Rx) CK high to FS (wl) low SRXD setup time before (Rx) CK low SRXD hold time after (Rx) CK low 81.4 36.0 - 36.0 - - - - - 10.0 0 - - 6 - 6 15.0 15.0 15.0 15.0 - - ns ns ns ns ns ns ns ns ns ns ns Parameter Min Max Unit Oversampling Clock Operation SS47 SS48 SS49 SS50 SS51 Oversampling clock period Oversampling clock high period Oversampling clock rise time Oversampling clock low period Oversampling clock fall time 15.04 6 - 6 - - - 3 - 3 ns ns ns ns ns NOTE All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. NOTE All timings are on AUDMUX pads when SSI is being used for data transfer. NOTE "Tx" and "Rx" refer to the Transmit and Receive sections of the SSI. NOTE For internal Frame Sync operation using external clock, the FS timing is the same as that of Tx Data, for example, during the AC97 mode of operation. i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 147 Electrical Characteristics 4.3.22.3 SSI Transmitter Timing with External Clock Figure 85 depicts the SSI transmitter timing with external clock, and Table 63 lists the timing parameters. SS22 SS23 SS25 SS26 SS24 AD1_TXC (Input) SS27 AD1_TXFS (bl) (Input) SS31 AD1_TXFS (wl) (Input) SS39 SS37 AD1_TXD (Output) SS45 SS44 AD1_RXD (Input) Note: SRXD Input in Synchronous mode only SS46 SS38 SS29 SS33 SS22 SS26 SS23 DAM1_T_CLK (Input) SS27 DAM1_T_FS (bl) (Input) SS31 DAM1_T_FS (wl) (Input) SS39 SS37 DAM1_TXD (Output) SS44 DAM1_RXD (Input) Note: SRXD Input in Synchronous mode only SS46 SS45 SS38 SS29 SS25 SS24 SS33 Figure 85. SSI Transmitter with External Clock Timing Diagram i.MX31/i.MX31L Advance Information, Rev. 1.4 148 Preliminary Freescale Semiconductor Electrical Characteristics Table 63. SSI Transmitter with External Clock Timing Parameters ID External Clock Operation SS22 SS23 SS24 SS25 SS26 SS27 SS29 SS31 SS33 SS37 SS38 SS39 (Tx/Rx) CK clock period (Tx/Rx) CK clock high period (Tx/Rx) CK clock rise time (Tx/Rx) CK clock low period (Tx/Rx) CK clock fall time (Tx) CK high to FS (bl) high (Tx) CK high to FS (bl) low (Tx) CK high to FS (wl) high (Tx) CK high to FS (wl) low (Tx) CK high to STXD valid from high impedance (Tx) CK high to STXD high/low (Tx) CK high to STXD high impedance 81.4 36.0 - 36.0 - -10.0 10.0 -10.0 10.0 - - - - - 6.0 - 6.0 15.0 - 15.0 - 15.0 15.0 15.0 ns ns ns ns ns ns ns ns ns ns ns ns Parameter Min Max Unit Synchronous External Clock Operation SS44 SS45 SS46 SRXD setup before (Tx) CK falling SRXD hold after (Tx) CK falling SRXD rise/fall time 10.0 2.0 - - - 6.0 ns ns ns NOTE All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. NOTE All timings are on AUDMUX pads when the SSI is being used for data transfer. NOTE "Tx" and "Rx" refer to the Transmit and Receive sections of the SSI. NOTE For internal Frame Sync operation using external clock, the FS timing will be same as that of Tx Data, for example, during the AC97 mode of operation. i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 149 Electrical Characteristics 4.3.22.4 SSI Receiver Timing with External Clock Figure 86 depicts the SSI receiver timing with external clock, and Table 64 lists the timing parameters. SS22 SS26 SS23 SS25 SS24 AD1_TXC (Input) SS28 AD1_TXFS (bl) (Input) SS32 AD1_TXFS (wl) (Input) SS35 SS41 SS40 AD1_RXD (Input) SS36 SS34 SS30 SS22 SS26 SS23 SS25 SS24 DAM1_T_CLK (Input) SS28 DAM1_T_FS (bl) (Input) DAM1_T_FS (wl) (Input) SS30 SS32 SS35 SS41 SS40 SS36 SS34 DAM1_RXD (Input) Figure 86. SSI Receiver with External Clock Timing Diagram Table 64. SSI Receiver with External Clock Timing Parameters ID External Clock Operation SS22 SS23 SS24 (Tx/Rx) CK clock period (Tx/Rx) CK clock high period (Tx/Rx) CK clock rise time 81.4 36.0 - - - 6.0 ns ns ns Parameter Min Max Unit i.MX31/i.MX31L Advance Information, Rev. 1.4 150 Preliminary Freescale Semiconductor Electrical Characteristics Table 64. SSI Receiver with External Clock Timing Parameters (continued) ID SS25 SS26 SS28 SS30 SS32 SS34 SS35 SS36 SS40 SS41 Parameter (Tx/Rx) CK clock low period (Tx/Rx) CK clock fall time (Rx) CK high to FS (bl) high (Rx) CK high to FS (bl) low (Rx) CK high to FS (wl) high (Rx) CK high to FS (wl) low (Tx/Rx) External FS rise time (Tx/Rx) External FS fall time SRXD setup time before (Rx) CK low SRXD hold time after (Rx) CK low Min 36.0 - -10.0 10.0 -10.0 10.0 - - 10.0 2.0 Max - 6.0 15.0 - 15.0 - 6.0 6.0 - - Unit ns ns ns ns ns ns ns ns ns ns NOTE All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. NOTE All timings are on AUDMUX pads when the SSI is being used for data transfer. NOTE "Tx" and "Rx" refer to the Transmit and Receive sections of the SSI. NOTE For internal Frame Sync operation using external clock, the FS timing will be same as that of Tx Data, for example, during the AC97 mode of operation. 4.3.23 USB Electrical Specifications This section describes the electrical information of the USBOTG port. The OTG port supports both serial and parallel interfaces. The high speed (HS) interface is supported via the ULPI (Ultra Low Pin Count Interface). Figure 87 depicts the USB ULPI timing diagram, and Table 65 lists the timing parameters. i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 151 Package Information and Pinout Clock TSC Control out (stp) TSD Data out TDC Control in (dir, nxt) TDD Data in TDC THD THC Figure 87. USB ULPI Interface Timing Diagram Table 65. USB ULPI Interface Timing Specification1 Parameter Setup time (control in, 8-bit data in) Hold time (control in, 8-bit data in) Output delay (control out, 8-bit data out) 1 Symbol Min 6.0 0.0 9.0 Max Units ns ns ns TSC, TSD THC, THD TDC, TDD Timing parameters are given as viewed by transceiver side. 5 Package Information and Pinout This section includes the following: * Pin/contact assignment information--usually in the form of a pin-out or contact connection diagram--for every applicable package, unless this information appears in Section 3, "Signal Descriptions." NOTE: Either pin or contact is used throughout the data sheet, as appropriate for the device. * * Mechanical package drawing for every applicable package Ordering information (if this information isn't included on page 1). The i.MX31 and i.MX31L devices are available in the following package: * 457 MAPBGA 14 x 14 mm 0.5 mm pitch package for production (Figure 88). i.MX31/i.MX31L Advance Information, Rev. 1.4 152 Preliminary Freescale Semiconductor Package Information and Pinout 5.1 MAPBGA Production Package 457 14 x 14 mm, 0.5 P See Figure 88 for package drawings and dimensions of the production package. i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 153 Package Information and Pinout 5.1.1 Production Package Outline Drawing Figure 88. Production Package: Mechanical Drawing i.MX31/i.MX31L Advance Information, Rev. 1.4 154 Preliminary Freescale Semiconductor Package Information and Pinout 5.1.2 MAPBGA Pinout for Production Package Figure 89 shows the i.MX31/i.MX31L ball map of pad locations. i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 155 156 i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary Package Information and Pinout A 1 GND 2 GND B GND GND C GND GND 4 5 6 CSPI2 CSPI2_ USBOT _MISO SS2 G_DAT A7 STXD4 SRXD CSPI2_ CSPI2_ 5 SS0 SPI_R DY SRXD4 SCK4 STXD5 CSPI2_ SS1 SCK5 CSPI2_ MOSI SFS4 NVCC5 3 SFS5 7 USBOT G_DAT A3 USBOT G_DAT A5 CSPI2_ SCLK 8 9 10 11 12 13 14 15 16 17 18 19 USBOT USB_B RXD1 G_NXT YP USBOT G_DAT A1 USBOT G_DAT A4 DSR_D DSR_D RXD2 CE1 TE1 CE_CO KEY_R KEY_R KEY_C KEY_C TDO NTROL OW3 OW7 OL3 OL7 KEY_R KEY_R KEY_C KEY_C TCK OW1 OW5 OL1 OL5 DE USBOT USB_P CTS1 G_DIR WR DCD_D DCD_D RTS2 CE1 TE1 20 21 22 23 24 25 SJC_M SVEN0 CAPTU GPIO1_ WATCH GND OD RE 6 DOG_R ST TRSTB SRX0 SCLK0 GPIO1_ GPIO1_ GND 1 5 GND GND 26 GND A GND B USBOT USB_O DTR_D DTR_D TXD2 G_STP C CE1 TE1 KEY_R KEY_C KEY_C RTCK OW2 OL0 OL4 SRST0 GPIO1 BOOT_ BOOT_ CLKO _2 MODE1 MODE3 GND C D E F CSPI3_ MOSI CSPI3_ ATA_DI SCLK OR ATA_D ATA_C MACK S1 GND GND NVCC5 BATT_ USBOT USBOT TXD1 RI_DC DTR_D KEY_R KEY_R LINE G_DAT G_DAT E1 CE2 OW0 OW6 A6 A0 CSPI3_ NVCC5 USBOT USBOT RTS1 RI_DT CTS2 KEY_R SPI_R G_DAT G_CLK E1 OW4 DY A2 ATA_DI OW ATA_C PC_PO S0 E PC_BV D2 PC_WA IT SD1_D ATA0 USBH2 _NXT PC_VS 2 PC_CD 1 SD1_C LK USBH2 _DIR QVCC1 NVCC3 NVCC3 QVCC4 QVCC1 GND GND GND KEY_C TDI OL6 KEY_C TMS OL2 GPIO1 GPIO1 BOOT_ GND _0 _4 MODE 0 SIMPD COMP NVCC1 NVCC1 0 ARE CKIL QVCC1 QVCC1 NVCC8 NVCC8 QVCC NVCC6 NVCC6 NVCC9 NVCC6 QVCC QVCC QVCC QVCC GND GND GND GND GND GND GND GND RESET_ IN NVCC1 CSI_H GPIO3_ SYNC 0 NVCC4 NVCC4 CSI_D8 CSI_D4 QVCC NVCC7 CSI_D1 CSI_D1 4 2 SD_D_I FPSHIF T READ LCS1 VPG1 STX0 BOOT_ GND MODE2 GND DVFS0 CKIH BOOT_ MODE4 POWER _FAIL D E F GPIO1_ VSTBY 3 VPG0 CLKSS G PWMO PC_R W H J CSPI3_ MISO DVFS1 G PC_RS PC_BV ATA_R T D1 ESET PC_RE IOIS16 ADY SD1_D ATA3 SD1_C MD USBH2 _STP CSPI1_ SCLK PC_VS 1 K PC_CD 2 L SD1_D ATA1 M USBH2 _DATA0 N USBH2 _CLK P R T U I2C_DA T I2C_CL CSI_VS K YNC POR GPIO3_ 1 CSI_PIX CLK H J K L M N PC_P WRON SD1_D ATA2 USBH2 _DATA1 CSPI1_ SPI_R DY CSPI1_ CSPI1_ CSPI1_ SS1 MOSI SS0 STXD3 SCK3 STXD6 SCK6 NFRB SRXD3 SFS6 NVCC3 GND CSI_MC CSI_D5 CSI_D7 LK CSI_D6 CSI_D9 CSI_D1 1 CSI_D1 CSI_D1 CSI_D1 0 3 5 VSYNC HSYNC DRDY0 0 SD_D_ SD_D_I LCS0 CLK O CONTR WRITE VSYNC AST 3 LD0 LD6 LD10 LD15 EB1 FVCC RW SER_R D3_REV S D3_SPL LD1 LD3 LD7 LD11 LD14 LD5 LD9 LD12 LD16 CSPI1_ CSPI1_ SS2 MISO SFS3 NFCE D15 D9 D3 SRXD6 NFWE D11 D5 NVCC2 2 NVCC1 0 QVCC4 QVCC4 QVCC4 NVCC1 GND 0 NVCC1 GND 0 NVCC1 GND 0 GND GND GND GND GND GND GND GND GND NVCC7 NVCC7 NVCC7 QVCC P R T U V W Y AA AB AC AD AE AF D3_CL PAR_RS S LD4 LD2 SGND MGND UGND NFWP NFCLE D13 D7 D1 A4 A6 A11 A12 A7 A9 3 A13 A3 A5 4 A2 V NFALE NFRE W D14 D12 Y D10 D8 D4 D0 GND GND GND GND 2 QVCC QVCC QVCC QVCC SVCC MVCC UVCC GND TTM_P LD8 AD LD17 LD13 EB0 AA D6 AB D2 AC MA10 AD GND AE GND AF GND 1 IOQVD NVCC2 NVCC2 NVCC2 NVCC2 NVCC2 NVCC2 NVCC2 NVCC2 NVCC2 NVCC2 NVCC2 NVCC2 NVCC2 NVCC2 M_GRA D 2 2 2 2 2 2 2 1 1 1 NT NVCC2 SD31 SD28 SD27 SD23 SD21 SD18 SD16 SD13 SD9 SD7 SD5 SD3 SD2 DQM2 SDCLK 2 FGND OE BCLK FUSE_V M_REQ GND DD UEST ECB CS0 CS1 23 GND GND CS4 24 GND GND GND 25 GND GND GND 26 A8 A0 SDBA0 SDQS3 SD29 SD26 A24 7 SD24 A23 8 SD22 A22 9 SD25 SD20 A21 10 SDQS2 SD17 SD19 A20 11 SD15 SD12 SD11 A17 14 SD8 SD10 A16 15 SDQS0 SD4 SD6 A15 16 SD1 A14 17 SDBA1 SD30 A1 A25 5 6 SDQS1 SD14 A19 A18 12 13 SDCKE CS3 0 DQM3 DQM0 SDCLK CS2 LBA A10 RAS SDWE SDCKE CS5 1 18 19 20 21 22 SD0 DQM1 CAS Figure 89. i.MX31/i.MX31L Ball Map Package Information and Pinout Figure 66 shows the signal color and signal name legend. Table 66. Signal Color/Name Legend Color None Name Signal name as listed GND NVCC1 NVCC2 NVCC3 NVCC4 NVCC5 NVCC6 NVCC7 NVCC8 NVCC9 NVCC10 NVCC21 NVCC22 QVCC QVCC1 QVCC4 Table 67 shows the device pin list, sorted by signal identification, excluding pad locations for ground and power supply voltages. Table 67. i.MX31/i.MX31L 14 x 14 BGA (457 Signal ID by Pad Grid Location) Signal ID A0 A1 A10 A11 A12 A13 A14 A15 Pad Location AD6 AF5 AF18 AC3 AD3 AD4 AF17 AF16 i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 157 Package Information and Pinout Table 67. i.MX31/i.MX31L 14 x 14 BGA (457 Signal ID by Pad Grid Location) (continued) Signal ID A16 A17 A18 A19 A2 A20 A21 A22 A23 A24 A25 A3 A4 A5 A6 A7 A8 A9 ATA_CS0 ATA_CS1 ATA_DIOR ATA_DIOW ATA_DMACK ATA_RESET BATT_LINE BCLK BOOT_MODE0 BOOT_MODE1 BOOT_MODE2 BOOT_MODE3 BOOT_MODE4 CAPTURE CAS CE_CONTROL CKIH CKIL CLKO Pad Location AF15 AF14 AF13 AF12 AB5 AF11 AF10 AF9 AF8 AF7 AF6 AE4 AA3 AF4 AB3 AE3 AD5 AF3 J6 F2 E2 H6 F1 H3 F7 AB26 F20 C21 D24 C22 D26 A22 AD20 A14 F24 H21 C23 i.MX31/i.MX31L Advance Information, Rev. 1.4 158 Preliminary Freescale Semiconductor Package Information and Pinout Table 67. i.MX31/i.MX31L 14 x 14 BGA (457 Signal ID by Pad Grid Location) (continued) Signal ID CLKSS COMPARE CONTRAST CS0 CS1 CS2 CS3 CS4 CS5 CSI_D10 CSI_D11 CSI_D12 CSI_D13 CSI_D14 CSI_D15 CSI_D4 CSI_D5 CSI_D6 CSI_D7 CSI_D8 CSI_D9 CSI_HSYNC CSI_MCLK CSI_PIXCLK CSI_VSYNC CSPI1_MISO CSPI1_MOSI CSPI1_SCLK CSPI1_SPI_RDY CSPI1_SS0 CSPI1_SS1 CSPI1_SS2 CSPI2_MISO CSPI2_MOSI CSPI2_SCLK CSPI2_SPI_RDY CSPI2_SS0 Pad Location G26 G18 R24 AE23 AF23 AE21 AD22 AF24 AF22 M24 L26 M21 M25 M20 M26 L21 K25 L24 K26 L20 L25 K20 K24 J26 J25 P7 P2 N2 N3 P3 P1 P6 A4 E3 C7 B6 B5 i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 159 Package Information and Pinout Table 67. i.MX31/i.MX31L 14 x 14 BGA (457 Signal ID by Pad Grid Location) (continued) Signal ID CSPI2_SS1 CSPI2_SS2 CSPI3_MISO CSPI3_MOSI CSPI3_SCLK CSPI3_SPI_RDY CTS1 CTS2 D0 D1 D10 D11 D12 D13 D14 D15 D2 D3 D3_CLS D3_REV D3_SPL D4 D5 D6 D7 D8 D9 DCD_DCE1 DCD_DTE1 DE DQM0 DQM1 DQM2 DQM3 DRDY0 DSR_DCE1 DSR_DTE1 Pad Location C6 A5 G3 D2 E1 G6 B11 G13 AB2 Y3 Y1 U7 W2 V3 W1 U6 AB1 W6 R20 T26 U25 AA2 V7 AA1 W3 Y2 V6 B12 B13 C18 AE19 AD19 AA20 AE18 N26 A11 A12 i.MX31/i.MX31L Advance Information, Rev. 1.4 160 Preliminary Freescale Semiconductor Package Information and Pinout Table 67. i.MX31/i.MX31L 14 x 14 BGA (457 Signal ID by Pad Grid Location) (continued) Signal ID DTR_DCE1 DTR_DCE2 DTR_DTE1 DVFS0 DVFS1 EB0 EB1 ECB FGND FPSHIFT FUSE_VDD FVCC GPIO1_0 GPIO1_1 GPIO1_2 GPIO1_3 GPIO1_4 GPIO1_5 GPIO1_6 GPIO3_0 GPIO3_1 HSYNC I2C_CLK I2C_DAT IOIS16 IOQVDD KEY_COL0 KEY_COL1 KEY_COL2 KEY_COL3 KEY_COL4 KEY_COL5 KEY_COL6 KEY_COL7 KEY_ROW0 KEY_ROW1 KEY_ROW2 Pad Location C11 F12 C12 E25 G24 W21 Y24 AD23 AB24 N21 AC24 AA24 F18 B23 C20 F25 F19 B24 A23 K21 H26 N25 J24 H25 J3 Y6 C15 B17 G15 A17 C16 B18 F15 A18 F13 B15 C14 i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 161 Package Information and Pinout Table 67. i.MX31/i.MX31L 14 x 14 BGA (457 Signal ID by Pad Grid Location) (continued) Signal ID KEY_ROW3 KEY_ROW4 KEY_ROW5 KEY_ROW6 KEY_ROW7 LBA LCS0 LCS1 LD0 LD1 LD10 LD11 LD12 LD13 LD14 LD15 LD16 LD17 LD2 LD3 LD4 LD5 LD6 LD7 LD8 LD9 M_GRANT M_REQUEST MA10 MGND MVCC NFALE NFCE NFCLE NFRB NFRE NFWE Pad Location A15 G14 B16 F14 A16 AE22 P26 P21 T24 U26 V24 Y25 Y26 V21 AA25 W24 AA26 V20 T21 V25 T20 V26 U24 W25 U21 W26 Y21 AC25 AC1 T15 V15 V1 T6 U3 U1 V2 T7 i.MX31/i.MX31L Advance Information, Rev. 1.4 162 Preliminary Freescale Semiconductor Package Information and Pinout Table 67. i.MX31/i.MX31L 14 x 14 BGA (457 Signal ID by Pad Grid Location) (continued) Signal ID NFWP NVCC9 OE PAR_RS PC_BVD1 PC_BVD2 PC_CD1 PC_CD2 PC_POE PC_PWRON PC_READY PC_RST PC_RW PC_VS1 PC_VS2 PC_WAIT POR POWER_FAIL PWMO RAS READ RESET_IN RI_DCE1 RI_DTE1 RTCK RTS1 RTS2 RW RXD1 RXD2 SCK3 SCK4 SCK5 SCK6 SCLK0 SD_D_CLK SD_D_I Pad Location U2 J17 AB25 R21 H2 K6 L7 K1 J7 K3 J2 H1 G2 J1 K7 L6 H24 E26 G1 AF19 P20 J21 F11 G12 C17 G11 B14 AB22 A10 A13 R2 C4 D3 T2 B22 P24 N20 i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 163 Package Information and Pinout Table 67. i.MX31/i.MX31L 14 x 14 BGA (457 Signal ID by Pad Grid Location) (continued) Signal ID SD_D_IO SD0 SD1 SD1_CLK SD1_CMD SD1_DATA0 SD1_DATA1 SD1_DATA2 SD1_DATA3 SD10 SD11 SD12 SD13 SD14 SD15 SD16 SD17 SD18 SD19 SD2 SD20 SD21 SD22 SD23 SD24 SD25 SD26 SD27 SD28 SD29 SD3 SD30 SD31 SD4 SD5 SD6 SD7 Pad Location P25 AD18 AE17 M7 L2 M6 L1 L3 K2 AE15 AE14 AD14 AA14 AE13 AD13 AA13 AD12 AA12 AE11 AA19 AE10 AA11 AE9 AA10 AE8 AD10 AE7 AA9 AA8 AD9 AA18 AE6 AA7 AD17 AA17 AE16 AA16 i.MX31/i.MX31L Advance Information, Rev. 1.4 164 Preliminary Freescale Semiconductor Package Information and Pinout Table 67. i.MX31/i.MX31L 14 x 14 BGA (457 Signal ID by Pad Grid Location) (continued) Signal ID SD8 SD9 SDBA0 SDBA1 SDCKE0 SDCKE1 SDCLK SDCLK SDQS0 SDQS1 SDQS2 SDQS3 SDWE SER_RS SFS3 SFS4 SFS5 SFS6 SGND SIMPD0 SJC_MOD SRST0 SRX0 SRXD3 SRXD4 SRXD5 SRXD6 STX0 STXD3 STXD4 STXD5 STXD6 SVCC SVEN0 TCK TDI TDO Pad Location AD15 AA15 AD7 AE5 AD21 AF21 AA21 AE20 AD16 AE12 AD11 AD8 AF20 T25 R6 F3 A3 T3 T14 G17 A20 C19 B21 R3 C3 B4 R7 F17 R1 B3 C5 T1 V14 A21 B19 F16 A19 i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 165 Package Information and Pinout Table 67. i.MX31/i.MX31L 14 x 14 BGA (457 Signal ID by Pad Grid Location) (continued) Signal ID TMS TRSTB TTM_PAD TXD1 TXD2 UVCC USB_BYP USB_OC USB_PWR USBH2_CLK USBH2_DATA0 USBH2_DATA1 USBH2_DIR USBH2_NXT USBH2_STP USBOTG_CLK USBOTG_DATA0 USBOTG_DATA1 USBOTG_DATA2 USBOTG_DATA3 USBOTG_DATA4 USBOTG_DATA5 USBOTG_DATA6 USBOTG_DATA7 USBOTG_DIR USBOTG_NXT USBOTG_STP UGND VPG0 VPG1 VSTBY VSYNC0 VSYNC3 WATCHDOG_RST WRITE Pad Location G16 B20 U20 F10 C13 V16 A9 C10 B10 N1 M1 M3 N7 N6 M2 G10 F9 B8 G9 A7 C8 B7 F8 A6 B9 A8 C9 T16 G25 J20 F26 N24 R26 A24 R25 i.MX31/i.MX31L Advance Information, Rev. 1.4 166 Preliminary Freescale Semiconductor Product Documentation 6 Product Documentation This Data Sheet is labeled as a particular type: Product Preview, Advance Information, or Technical Data. Definitions of these types are available at: http://www.freescale.com. 6.1 Revision History Table 68. Revision History Location Revision Core Supply voltage--changed minimum voltage FROM 1.2 V TO 1.22 V. * Min (V) for 1st row--changed value FROM 1.2 V to 1.22 V. * Added footnotes. Updated entire table. Updated DPLL section for content. Replaced HI/LO with content about external clock source (CKIH) and FPM (Frequency Pre-Multiplier). * Changed SD4, SD6 min values FROM 1.8 V TO 2.0 V. * Changed SD13 min value FROM 2.4 V TO 2.0 V. Table 68 summarizes revisions to this document since the release of Rev. 1.2. Table 9, "DC Recommended Operating Conditions," on page 61 Table 10, "Voltage versus Core Frequency," on page 62 Table 13, "Power Consumption (Typical Values)," on page 64 Section 4.3.8, "DPLL Electrical Specifications" starting on page 82 Table 34, "DDR/SDR SDRAM Read Cycle Timing Parameters," on page 94, Table 35, "SDR SDRAM Write Timing Parameters," on page 96 Section 4.3.10, "ETM Electrical At ETM Trace Data Timing Parameters table: Changed Ts Setup value FROM 3 Specifications" on page 100, Table 41, "ETM TO 2, changed Th Hold value FROM 2 TO 1. Trace Data Timing Parameters," on page 101. Table 60, "SJC Timing Parameters," on page 143 * SJ1 row--Removed "in Crystal mode", changed min value FROM 45.0 ns TO 100.0 ns. * Changed SJ2 min value FROM 22.5 ns TO 40.0 ns. * Changed SJ4 min value FROM 5.0 ns TO 10.0 ns. * Changed SJ5 min value FROM 24.0 ns TO 50.0 ns. * Changed SJ8 min value FROM 5.0 ns TO 10.0 ns. * Changed SJ9 min value FROM 25.0 ns TO 50.0 ns. Updated section for figure, table values. Updated section. Section 4.3.2, "AC Electrical Characteristics" starting on page 68 Section 2.1.1, "Performance" on page 4 Table 11, "Interface Frequency," on page 62 Updated. Section 4.3.23, "USB Electrical Specifications" on page 151 Figure 89, "i.MX31/i.MX31L Ball Map," on page 156 Revised section; added ULPI information. Revised for color, grid # ID. i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 167 Product Documentation Table 68. Revision History (continued) Location Table 23, "ATA Timing Parameters," on page 72 Revision * Inserted the following values: * ti_ds, 11 ns * ti_dh, 6 ns * tco, 15 ns * tsu, 19 ns * tsui, 9 ns * thi, 5 ns * Changed tskew1 value FROM 20 ns TO 7 ns. Changed CS4, CS5, CS6 min values FROM 30 ns TO 25 ns. Updated entire table. Changed IP18 min value FROM Tdicd-1.5 TO Tdicd-3.5. Changed IP19 min value FROM Tdicp-Tdicd-1.5 TO Tdicp-Tdicd-3.5. Changed IP20 min value FROM Tdicd-1.5 TO Tdicd-3.5. Changed pad voltage FROM 1.7 V TO 1.75 V. Table 29, "CSPI Interface Timing Parameters," on page 81 Table 33, "WEIM Bus Timing Parameters," on page 89 Table 49, "Synchronous Display Interface Timing Parameters--Access Level," on page 110 Above Figure 30, "Asynchronous Memory Timing Diagram for Read Access--WSC=1," on page 91 Section 4.1, "i.MX31 and i.MX31L Chip-Level Conditions" starting on page 60 * Table 9, "DC Recommended Operating Conditions," on page 61--changed Core Supply Voltage row max voltage FROM 1.6 V to 1.65 V, footnote value FROM 1.6 V TO 1.65 V (2 plcs). * Table 10, "Voltage versus Core Frequency," on page 62--changed both max values FROM 1.6 V TO 1.65 V; PMIC value in footnote FROM 1.575 V to 1.6 V. * Table 12, "DC Absolute Maximum Operating Conditions," on page 63--changed max value FROM 1.6 V to 1.65 V. Removed duplicate notes about pad voltages and signal values. Corrected pad locations for area of rows E through N, columns 4 through 26. Section 4.3.9.3, "SDRAM (DDR and SDR) Memory Controller" starting on page 93 Figure 89, "i.MX31/i.MX31L Ball Map," on page 156 i.MX31/i.MX31L Advance Information, Rev. 1.4 168 Preliminary Freescale Semiconductor Product Documentation i.MX31/i.MX31L Advance Information, Rev. 1.4 Freescale Semiconductor Preliminary 169 How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064, Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-521-6274 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. ARM, ARM Thumb, Jazelle, and the ARM Powered logo are registered trademarks of ARM Limited. ARM1136JF-S, ARM11, Embedded Trace Kit, Embedded Trace Macrocell, ETM, Embedded Trace Buffer, and ETB are trademarks of ARM Limited. All other product or service names are the property of their respective owners. Java and all other Java-based marks are trademarks or registered trademarks of Sun Microsystems, Inc. in the U.S. and other countries. France Telecom - TDF - Groupe des ecoles des telecommunications Turbo codes patents license. (c) Freescale Semiconductor, Inc. 2005, 2006. All rights reserved. Document Number: MCIMX31 Rev. 1.4 04/2006 Preliminary |
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